diff options
author | Iru Cai <mytbk920423@gmail.com> | 2017-07-07 21:44:42 +0800 |
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committer | Martin Roth <martinroth@google.com> | 2017-08-18 15:31:08 +0000 |
commit | 6f08ef9bdaec2a81cd6d70192aa37bda2ace6640 (patch) | |
tree | 227823f5c204fe244f251126c798c7fc3e730b49 /src/mainboard/hp/2570p/romstage.c | |
parent | df48d8b2c26874196d9d9511408c493ae1f23d13 (diff) |
mainboard/hp: Add HP Elitebook 2570p
The code is based on autoport. The EHCI debug port is the upper USB
port beside the battery.
Tested and working:
- CPU and memory: i7-3720QM, 4G+4G
- Linux Mint with Linux 4.4 (SeaBIOS payload)
- All USB ports
- ExpressCard
- WLAN
- AC and battery status
- S3
- Other devices detected: DVD drive, smartcard reader, fingerprint, bluetooth
Not tested:
- VGA and DP
- Ethernet and modem
- Dock
Change-Id: I9f3cd124fc676d49add59e9f0a07f70a6bb0fff0
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/hp/2570p/romstage.c')
-rw-r--r-- | src/mainboard/hp/2570p/romstage.c | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c new file mode 100644 index 0000000000..53b44b6c8f --- /dev/null +++ b/src/mainboard/hp/2570p/romstage.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/hp/kbc1126/ec.h> + +void pch_enable_lpc(void) +{ + /* + * CNF2 and CNF1 for Super I/O + * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); + /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); +} + +void rcba_config(void) +{ + RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0; +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 0, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 0, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 1, 0, 5 }, + { 0, 0, 5 }, + { 1, 0, 6 }, + { 0, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); + kbc1126_disable4e(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} |