ChromeOS: Refactor ACPI CNVS generation

Remove chromeos_dsdt_generator() calls under mainboard, it
is possible to make the single call to fill \CNVS and
\OIPG without leveraging device operations.

Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

26 files changed, 0 insertions, 67 deletions

diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c
index 12d5a68da6..f465d0775d 100644
--- a/src/mainboard/google/auron/mainboard.c
+++ b/src/mainboard/google/auron/mainboard.c
@@ -2,7 +2,6 @@
 
 #include <device/device.h>
 #include <drivers/intel/gma/int15.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 #include "variant.h"
 
@@ -29,7 +28,6 @@ static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = mainboard_smbios_data;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 
diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c
index 7eba3c2c2f..b35e005405 100644
--- a/src/mainboard/google/beltino/mainboard.c
+++ b/src/mainboard/google/beltino/mainboard.c
@@ -4,7 +4,6 @@
 #include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "onboard.h"
 
@@ -25,7 +24,6 @@ static void mainboard_init(struct device *dev)
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c
index 6287d2ceb5..b07a15166f 100644
--- a/src/mainboard/google/brya/mainboard.c
+++ b/src/mainboard/google/brya/mainboard.c
@@ -5,7 +5,6 @@
 #include <device/device.h>
 #include <ec/ec.h>
 #include <soc/ramstage.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <fw_config.h>
 
 static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
@@ -60,7 +59,6 @@ static void mainboard_dev_init(struct device *dev)
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_dev_init;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 	dev->ops->get_smbios_strings = mainboard_smbios_strings;
 }
 
diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c
index 6145dc73d4..87ce61f2e1 100644
--- a/src/mainboard/google/butterfly/mainboard.c
+++ b/src/mainboard/google/butterfly/mainboard.c
@@ -14,7 +14,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <smbios.h>
 #include <ec/quanta/ene_kb3940q/ec.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 static unsigned int search(char *p, char *a, unsigned int lengthp,
 			   unsigned int lengtha)
@@ -258,7 +257,6 @@ static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = butterfly_onboard_smbios_data;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 
diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c
index b8266b31dc..1e0006ce01 100644
--- a/src/mainboard/google/cyan/mainboard.c
+++ b/src/mainboard/google/cyan/mainboard.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 
 static void mainboard_init(struct device *dev)
@@ -16,7 +15,6 @@ static void mainboard_init(struct device *dev)
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c
index dba4795293..700b3e368a 100644
--- a/src/mainboard/google/dedede/mainboard.c
+++ b/src/mainboard/google/dedede/mainboard.c
@@ -9,7 +9,6 @@
 #include <security/tpm/tss.h>
 #include <soc/soc_chip.h>
 #include <vb2_api.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 static void mainboard_update_soc_chip_config(void)
 {
@@ -68,7 +67,6 @@ static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_dev_init;
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/deltaur/mainboard.c b/src/mainboard/google/deltaur/mainboard.c
index e1cdb96959..9812d9fea5 100644
--- a/src/mainboard/google/deltaur/mainboard.c
+++ b/src/mainboard/google/deltaur/mainboard.c
@@ -4,14 +4,8 @@
 #include <baseboard/variants.h>
 #include <device/device.h>
 #include <soc/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <variant/gpio.h>
 
-static void mainboard_enable(struct device *dev)
-{
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
-}
-
 static void mainboard_chip_init(void *chip_info)
 {
 	const struct pad_config *base_pads;
@@ -26,5 +20,4 @@ static void mainboard_chip_init(void *chip_info)
 
 struct chip_operations mainboard_ops = {
 	.init = mainboard_chip_init,
-	.enable_dev = mainboard_enable,
 };
diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c
index d44c7b19d3..7c34c0d5c4 100644
--- a/src/mainboard/google/drallion/ramstage.c
+++ b/src/mainboard/google/drallion/ramstage.c
@@ -4,7 +4,6 @@
 #include <smbios.h>
 #include <soc/ramstage.h>
 #include <variant/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /* mainboard silk screen shows DIMM-A and DIMM-B */
 void smbios_fill_dimm_locator(const struct dimm_info *dimm,
@@ -32,12 +31,6 @@ static void mainboard_init(void *chip_info)
 	gpio_configure_pads(gpio_table, num_gpios);
 }
 
-static void mainboard_enable(struct device *dev)
-{
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
-}
-
 struct chip_operations mainboard_ops = {
 	.init = mainboard_init,
-	.enable_dev = mainboard_enable,
 };
diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c
index 35c0a61953..4abb91e57f 100644
--- a/src/mainboard/google/eve/mainboard.c
+++ b/src/mainboard/google/eve/mainboard.c
@@ -4,7 +4,6 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <ec/ec.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/nhlt.h>
 
 #include "gpio.h"
@@ -58,7 +57,6 @@ static unsigned long mainboard_write_acpi_tables(
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
 }
 
diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c
index 307faddbe6..13bc9b70ca 100644
--- a/src/mainboard/google/fizz/mainboard.c
+++ b/src/mainboard/google/fizz/mainboard.c
@@ -17,7 +17,6 @@
 #include <soc/nhlt.h>
 #include <string.h>
 #include <timer.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include <variant/gpio.h>
 
@@ -223,7 +222,6 @@ static void mainboard_enable(struct device *dev)
 	mainboard_set_power_limits(soc_conf);
 
 	dev->ops->init = mainboard_init;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
 }
 
diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c
index 0d6a49942e..faa80b9cbb 100644
--- a/src/mainboard/google/glados/mainboard.c
+++ b/src/mainboard/google/glados/mainboard.c
@@ -7,7 +7,6 @@
 #include <gpio.h>
 #include <soc/nhlt.h>
 #include <variant/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 
 static const char *oem_id_maxim = "INTEL";
@@ -96,7 +95,6 @@ static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 }
 
 static void mainboard_chip_init(void *chip_info)
diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c
index c50304dd5b..cab570672d 100644
--- a/src/mainboard/google/guybrush/mainboard.c
+++ b/src/mainboard/google/guybrush/mainboard.c
@@ -10,7 +10,6 @@
 #include <gpio.h>
 #include <soc/acpi.h>
 #include <variant/ec.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #define BACKLIGHT_GPIO			GPIO_129
 #define WWAN_AUX_RST_GPIO		GPIO_18
@@ -197,7 +196,6 @@ static void mainboard_enable(struct device *dev)
 {
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
 
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 
 	init_tables();
diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c
index 93864b2ad1..86065f95d3 100644
--- a/src/mainboard/google/hatch/ramstage.c
+++ b/src/mainboard/google/hatch/ramstage.c
@@ -6,7 +6,6 @@
 #include <soc/gpio.h>
 #include <soc/ramstage.h>
 #include <variant/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 void mainboard_silicon_init_params(FSPS_UPD *supd)
 {
@@ -36,7 +35,6 @@ static void mainboard_init(struct device *dev)
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 	variant_mainboard_enable(dev);
 }
 
diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c
index fd7e9e2493..3c255b7871 100644
--- a/src/mainboard/google/jecht/mainboard.c
+++ b/src/mainboard/google/jecht/mainboard.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
 
 static void mainboard_init(struct device *dev)
@@ -15,7 +14,6 @@ static void mainboard_init(struct device *dev)
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index e54ac742bf..2cd88b87f8 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -17,7 +17,6 @@
 #include <amdblocks/acpimmio.h>
 #include <variant/ec.h>
 #include <variant/thermal.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /***********************************************************
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@@ -147,7 +146,6 @@ static void mainboard_enable(struct device *dev)
 	/* Initialize the PIRQ data structures for consumption */
 	pirq_setup();
 
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 }
 
 int mainboard_get_xhci_oc_map(uint16_t *map)
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index c4b621ac7a..4c98761685 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -16,7 +16,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <smbios.h>
 #include <ec/google/chromeec/ec.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #if CONFIG(VGA_ROM_RUN)
 static int int15_handler(void)
@@ -170,7 +169,6 @@ static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = link_onboard_smbios_data;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 #if CONFIG(VGA_ROM_RUN)
 	/* Install custom int15 handler for VGA OPROM */
 	mainboard_interrupt_handlers(0x15, &int15_handler);
diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c
index fbebe576fc..a614763bda 100644
--- a/src/mainboard/google/octopus/mainboard.c
+++ b/src/mainboard/google/octopus/mainboard.c
@@ -20,7 +20,6 @@
 #include <soc/nhlt.h>
 #include <soc/pci_devs.h>
 #include <stdint.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <variant/ec.h>
 #include <variant/gpio.h>
 
@@ -140,7 +139,6 @@ static unsigned long mainboard_write_acpi_tables(
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c
index 16695dbeb8..eeb3ce4487 100644
--- a/src/mainboard/google/parrot/mainboard.c
+++ b/src/mainboard/google/parrot/mainboard.c
@@ -10,7 +10,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <smbios.h>
 #include <ec/compal/ene932/ec.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 void mainboard_suspend_resume(void)
 {
@@ -61,7 +60,6 @@ static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = parrot_onboard_smbios_data;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 
diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c
index 0a3fe1ff0f..0e6c7b98c6 100644
--- a/src/mainboard/google/poppy/mainboard.c
+++ b/src/mainboard/google/poppy/mainboard.c
@@ -6,7 +6,6 @@
 #include <ec/ec.h>
 #include <soc/pci_devs.h>
 #include <soc/nhlt.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include <variant/gpio.h>
 
@@ -47,7 +46,6 @@ static unsigned long mainboard_write_acpi_tables(const struct device *device,
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
 }
 
diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c
index ef1acbdc59..257b8fab6c 100644
--- a/src/mainboard/google/rambi/mainboard.c
+++ b/src/mainboard/google/rambi/mainboard.c
@@ -8,7 +8,6 @@
 #include <soc/gpio.h>
 #include <soc/int15.h>
 #include <bootstate.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 static void mainboard_init(struct device *dev)
 {
@@ -54,7 +53,6 @@ static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = mainboard_smbios_data;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 
 	/* Install custom int15 handler for VGA OPROM */
 	if (CONFIG(VGA_ROM_RUN))
diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c
index e0078805ee..8cae9592d7 100644
--- a/src/mainboard/google/reef/mainboard.c
+++ b/src/mainboard/google/reef/mainboard.c
@@ -12,7 +12,6 @@
 #include <soc/gpio.h>
 #include <soc/nhlt.h>
 #include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <variant/ec.h>
 #include <variant/gpio.h>
 
@@ -125,7 +124,6 @@ static unsigned long mainboard_write_acpi_tables(
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c
index 6287628a88..8d619db5a7 100644
--- a/src/mainboard/google/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/ramstage.c
@@ -5,7 +5,6 @@
 #include <smbios.h>
 #include <soc/gpio.h>
 #include <variant/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #if CONFIG(GENERATE_SMBIOS_TABLES)
 /* mainboard silk screen shows DIMM-A and DIMM-B */
@@ -46,12 +45,6 @@ static void mainboard_init(void *chip_info)
 		gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused));
 }
 
-static void mainboard_enable(struct device *dev)
-{
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
-}
-
 struct chip_operations mainboard_ops = {
 	.init = mainboard_init,
-	.enable_dev = mainboard_enable,
 };
diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c
index 90f28e7ec2..47f071c2a4 100644
--- a/src/mainboard/google/slippy/mainboard.c
+++ b/src/mainboard/google/slippy/mainboard.c
@@ -6,7 +6,6 @@
 #include <drivers/intel/gma/int15.h>
 #include <acpi/acpi.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 #include "onboard.h"
 
@@ -66,7 +65,6 @@ static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = mainboard_smbios_data;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 
diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c
index 7f4e29d2e8..ae68a78dcb 100644
--- a/src/mainboard/google/stout/mainboard.c
+++ b/src/mainboard/google/stout/mainboard.c
@@ -6,7 +6,6 @@
 #include <acpi/acpi.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/quanta/it8518/ec.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "ec.h"
 #include "onboard.h"
@@ -42,7 +41,6 @@ static void mainboard_init(struct device *dev)
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c
index 9f8e646ae1..892da5185e 100644
--- a/src/mainboard/google/volteer/mainboard.c
+++ b/src/mainboard/google/volteer/mainboard.c
@@ -14,7 +14,6 @@
 #include <soc/gpio.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <variant/gpio.h>
 #include <vb2_api.h>
 
@@ -78,7 +77,6 @@ static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_init;
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 	dev->ops->get_smbios_strings = mainboard_smbios_strings;
 
 	variant_ramstage_init();
diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c
index ea292f163e..54da830004 100644
--- a/src/mainboard/google/zork/mainboard.c
+++ b/src/mainboard/google/zork/mainboard.c
@@ -23,7 +23,6 @@
 #include <amdblocks/acpimmio.h>
 #include <variant/ec.h>
 #include <variant/thermal.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <commonlib/helpers.h>
 
 #define METHOD_BACKLIGHT_ENABLE    "\\_SB.BKEN"
@@ -203,7 +202,6 @@ static void mainboard_enable(struct device *dev)
 	/* Initialize the PIRQ data structures for consumption */
 	pirq_setup();
 
-	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 
 }