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| author | Furquan Shaikh <furquan@google.com> | 2021-10-05 21:37:33 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2021-10-19 16:09:26 +0000 |
| commit | f888c682f80e950ef981251f3234569f3c367fc1 (patch) | |
| tree | 1d576b79ee595b2236652360f51e8d3f52b349c1 /src/mainboard/google | |
| parent | 6ef863c5c43aaccbc99c8518832e786f8cd5e9d1 (diff) | |
soc/intel/alderlake: Enable support for CSE stitching
This change enables support for stitching of BP1 and BP2 partitions
for CSE. This currently mimics what Intel FIT tool does w.r.t. adding
different components to the different partitions.
BP1:
* Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP.
* Decomposed components from CSE FPT file: RBEP, MFTP.
* Input components: PMCP, IOMP, NPHY, TBTP, PCHC.
BP2:
* Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP, ISHP.
* Decomposed components from CSE FPT file: RBEP, FTPR, NFTP.
* Input components: PMCP, IOMP, NPHY, TBTP, PCHC, IUNP.
BUG=b:189177580,b:189177538
Change-Id: I2b14405aab2a4919431d9c16bc7ff2eb1abf1f6b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
0 files changed, 0 insertions, 0 deletions