diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-03-29 15:34:07 +0200 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-04-02 06:27:50 +0000 |
| commit | f7f7b3bbf6827494985afae5f10312e63d6a8049 (patch) | |
| tree | f6f3bc60c9e05956cad4b6708b248a52fef83324 /src/mainboard/google | |
| parent | 3453c313acf7d1a6d26ef649b47dc1c3c0c7b677 (diff) | |
soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP
Add the 28W TDP version of the ADL-P with MCHID 0x4629.
Verified that all 28W SoCs have the same PL1/PL2 defined
in Intel document #655258 "12th Generation Intel Core
Processors Datasheet, Volume 1 of 2".
Fixes the error seen in coreboot log:
[ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration
Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Diffstat (limited to 'src/mainboard/google')
5 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/brya/variants/aurash/overridetree.cb b/src/mainboard/google/brya/variants/aurash/overridetree.cb index e40709494f..bd3e9d1254 100644 --- a/src/mainboard/google/brya/variants/aurash/overridetree.cb +++ b/src/mainboard/google/brya/variants/aurash/overridetree.cb @@ -50,7 +50,7 @@ chip soc/intel/alderlake .tdp_pl1_override = 15, .tdp_pl2_override = 25, }" - register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 64, }" device domain 0 on diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index faed00d04c..a6b1a087fb 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -87,7 +87,7 @@ chip soc/intel/alderlake register "tcc_offset" = "10" # TCC of 90 - register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 30, .tdp_pl2_override = 60, .tdp_pl4 = 90, diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 97682bd9d2..8b06732b74 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -83,7 +83,7 @@ chip soc/intel/alderlake }, }" - register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 20, .tdp_pl2_override = 43, .tdp_pl4 = 105, diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index ded70f2f50..cad69bb95f 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -51,7 +51,7 @@ chip soc/intel/alderlake register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ .tdp_pl1_override = 55, }" - register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 64, }" device domain 0 on diff --git a/src/mainboard/google/brya/variants/zydron/overridetree.cb b/src/mainboard/google/brya/variants/zydron/overridetree.cb index ed3595bb3a..49d8302ee1 100644 --- a/src/mainboard/google/brya/variants/zydron/overridetree.cb +++ b/src/mainboard/google/brya/variants/zydron/overridetree.cb @@ -83,7 +83,7 @@ chip soc/intel/alderlake }, }" - register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 20, .tdp_pl2_override = 43, .tdp_pl4 = 105, |