diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-02-16 19:17:29 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-18 14:56:15 +0000 |
| commit | f04faa149ffe4df7dd18391aa4e2eae9a6ceec73 (patch) | |
| tree | ab502c362e97f50a3308cdcaed9b7d67b15c845f /src/mainboard/google | |
| parent | b6d522f6c71f1664efc0cb6fc14af647f7dbaf6e (diff) | |
mb/google/brya/var/{taeko, taeko4es}: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie304b08b0b1bbad5547a0169ea8056d703141391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61830
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/taeko/overridetree.cb | 47 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/taeko4es/overridetree.cb | 42 |
2 files changed, 16 insertions, 73 deletions
diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index b70b05eac1..760ffa6e3f 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -459,24 +459,14 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on probe DB_USB DB_USB3_NO_A probe DB_USB DB_USB3_1C_1A @@ -492,24 +482,14 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on probe DB_USB DB_USB3_NO_A probe DB_USB DB_USB3_1C_1A @@ -524,6 +504,8 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port (DB)"" register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" register "group" = "ACPI_PLD_GROUP(3, 1)" device ref usb2_port7 on probe DB_USB DB_USB3_1C_1A @@ -533,12 +515,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -552,18 +529,14 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (DB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port3 on probe DB_USB DB_USB3_1C_1A end diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index b0a5de6517..11d572f96f 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -441,24 +441,14 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on probe DB_USB DB_USB3_NO_A end @@ -473,24 +463,14 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on probe DB_USB DB_USB3_NO_A end @@ -505,12 +485,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(3, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -524,12 +499,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(3, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port1 on end end end |