diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2018-09-21 14:59:22 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-09-26 21:22:27 +0000 |
| commit | e6e84f1ea963883927f7e8bed55a175a2a0552e9 (patch) | |
| tree | afac49770d0afa903f01528023bf0dc5b9a62bf4 /src/mainboard/google | |
| parent | aa69e2859df03229e4d48c36d914666544ba8eec (diff) | |
mb/google/poppy/variants/nocturne: Add tdp_pl1_override value
Add tdp_pl1_override value as 7W.
BUG=None
BRANCH=None
TEST=Build coreboot for Nocturne board
Change-Id: I16d3894da68bc3be6eff526062f9a88ef2df60c7
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/28708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 3359a77d51..70a379c799 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -66,6 +66,7 @@ chip soc/intel/skylake # Set speed_shift_enable to 1 to enable P-States, and 0 to disable register "speed_shift_enable" = "1" + register "tdp_pl1_override" = "7" register "tdp_pl2_override" = "18" register "psys_pmax" = "45" register "tcc_offset" = "10" |