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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-05 15:56:18 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-02-14 15:16:19 +0000
commitccb53e181726ddd90ec6d5a2b6d6b62ab8bd6a70 (patch)
tree93cab9d95f1c61d8bc2b77150f2669fe88089b5d /src/mainboard/google
parent9c790a2fdc1fdf98cbc8fe92a6662c475ce36bed (diff)
binaryPI: Fix cache coherency use for AP CPUs
The memory between _car_region_start .. _car_region_end has to be set up as WB in MTRRs for all the cores executing through bootblock, verstage and romstage. Otherwise global variables may fail on AP CPUs. Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n, which previously did not boot at all for some cases. Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/26115 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
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