mb/google/brya: Introduce new baseboard brask

This patch initiates the brask setting which includes
the gpio and device tree setting.

BUG=b:191472401
BRANCH=None
TEST=build pass

Change-Id: I1bb42c7bb2492402de0810bc4ab2e8d8c0e2392b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

13 files changed, 694 insertions, 9 deletions

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 3637959bf2..9279f4b9be 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -1,17 +1,27 @@
 config BOARD_GOOGLE_BASEBOARD_BRYA
 	def_bool n
+	select ROMSTAGE_SPD_CBFS
+	select SYSTEM_TYPE_LAPTOP
+
+config BOARD_GOOGLE_BASEBOARD_BRASK
+	def_bool n
+
+if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK
+
+config BOARD_GOOGLE_BRYA_COMMON
+	def_bool y
 	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GENERIC_MAX98357A
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
-	select DRIVERS_GENERIC_MAX98357A
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_INTEL_DPTF
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_SOUNDWIRE
 	select DRIVERS_INTEL_USB4_RETIMER
+	select DRIVERS_SPI_ACPI
 	select DRIVERS_SOUNDWIRE_ALC5682
 	select DRIVERS_SOUNDWIRE_MAX98373
-	select DRIVERS_SPI_ACPI
 	select DRIVERS_WIFI_GENERIC
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
@@ -23,7 +33,6 @@ config BOARD_GOOGLE_BASEBOARD_BRYA
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
-	select HAVE_SPD_IN_CBFS
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_I2C_TPM_CR50
@@ -31,13 +40,11 @@ config BOARD_GOOGLE_BASEBOARD_BRYA
 	select SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
 	select SOC_INTEL_CSE_LITE_SKU
-	select SYSTEM_TYPE_LAPTOP
-
-if BOARD_GOOGLE_BASEBOARD_BRYA
 
 config BASEBOARD_DIR
 	string
 	default "brya" if BOARD_GOOGLE_BASEBOARD_BRYA
+	default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK
 
 config CHROMEOS
 	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI
@@ -69,9 +76,11 @@ config MAINBOARD_DIR
 config MAINBOARD_FAMILY
 	string
 	default "Google_Brya" if BOARD_GOOGLE_BASEBOARD_BRYA
+	default "Google_Brask" if BOARD_GOOGLE_BASEBOARD_BRASK
 
 config MAINBOARD_PART_NUMBER
 	default "Brya" if BOARD_GOOGLE_BRYA0
+	default "Brask" if BOARD_GOOGLE_BRASK
 	default "Primus" if BOARD_GOOGLE_PRIMUS
 	default "Gimble" if BOARD_GOOGLE_GIMBLE
 	default "Redrix" if BOARD_GOOGLE_REDRIX
@@ -81,6 +90,7 @@ config MAINBOARD_PART_NUMBER
 
 config VARIANT_DIR
 	default "brya0" if BOARD_GOOGLE_BRYA0
+	default "brask" if BOARD_GOOGLE_BRASK
 	default "primus" if BOARD_GOOGLE_PRIMUS
 	default "gimble" if BOARD_GOOGLE_GIMBLE
 	default "redrix" if BOARD_GOOGLE_REDRIX
@@ -96,4 +106,8 @@ config UART_FOR_CONSOLE
 	int
 	default 0
 
-endif # BOARD_GOOGLE_BASEBOARD_BRYA
+config ROMSTAGE_SPD_CBFS
+	def_bool n
+	select HAVE_SPD_IN_CBFS
+
+endif # BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 72059ae026..bf4dc6d751 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -6,6 +6,12 @@ config BOARD_GOOGLE_BRYA0
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select SOC_INTEL_COMMON_BLOCK_IPU
 
+config BOARD_GOOGLE_BRASK
+	bool "Brask"
+	select BOARD_GOOGLE_BASEBOARD_BRASK
+	select ADL_ENABLE_USB4_PCIE_RESOURCES
+	select SOC_INTEL_CRASHLOG
+
 config BOARD_GOOGLE_PRIMUS
 	bool "-> Primus"
 	select BOARD_GOOGLE_BASEBOARD_BRYA
diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc
index 717cf5fe40..5dabd84bab 100644
--- a/src/mainboard/google/brya/Makefile.inc
+++ b/src/mainboard/google/brya/Makefile.inc
@@ -3,7 +3,7 @@ bootblock-y += bootblock.c
 verstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
-romstage-y += romstage.c
+romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c
 
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += mainboard.c
@@ -15,7 +15,8 @@ BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
 subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
 subdirs-y += variants/$(VARIANT_DIR)
 subdirs-y += variants/$(VARIANT_DIR)/memory
-subdirs-y += spd
+subdirs-$(CONFIG_ROMSTAGE_SPD_CBFS) += spd
 
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/brya/romstage.c b/src/mainboard/google/brya/romstage_spd_cbfs.c
index dc44c0d309..dc44c0d309 100644
--- a/src/mainboard/google/brya/romstage.c
+++ b/src/mainboard/google/brya/romstage_spd_cbfs.c
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc
new file mode 100644
index 0000000000..9fb63f5f43
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc
@@ -0,0 +1,3 @@
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
new file mode 100644
index 0000000000..b6dbf4dc5b
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -0,0 +1,150 @@
+chip soc/intel/alderlake
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "GPP_A"
+	register "pmc_gpe0_dw1" = "GPP_E"
+	register "pmc_gpe0_dw2" = "GPP_F"
+
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+        # S0ix enable
+        register "s0ix_enable" = "1"
+
+	# DPTF enable
+	register "dptf_enable" = "1"
+
+	# Enable heci communication
+	register "HeciEnabled" = "1"
+
+	# This disabled autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+
+	# Enable CNVi BT
+	register "CnviBtCore" = "true"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# USB2_C1
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"	# USB2_C2
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# NFC
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A3
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A2
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A1
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-A port A0
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A1(DCI)
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A2
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-A port A3
+
+	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
+	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)"
+	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)"
+
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+	}"
+
+	register "SerialIoGSpiMode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+	}"
+
+	register "SerialIoUartMode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	# HD Audio
+	register "PchHdaDspEnable" = "1"
+	register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
+	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
+	register "PchHdaIDispCodecEnable" = "1"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
+	#| GSPI1             | Fingerprint MCU           |
+	#| I2C0              | Audio                     |
+	#| I2C3              | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#+-------------------+---------------------------+
+	register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	device domain 0 on
+		device ref igpu on end
+		device ref dtt on end
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tbt_pcie_rp2 on end
+		device ref tcss_xhci on end
+		device ref tcss_dma0 on end
+		device ref tcss_dma1 on end
+		device ref xhci on end
+		device ref shared_sram on end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end
+		device ref heci1 on end
+		device ref sata on end
+		device ref pcie_rp8 on
+			# Enable SD Card PCIE 8 using clk 3
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end	#PCIE8 SD card
+		device ref uart0 on end
+		device ref gspi1 on end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref hda on end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
new file mode 100644
index 0000000000..f134431361
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
@@ -0,0 +1,424 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* A0 thru A5, A9 and A10 come configured out of reset, do not touch */
+	/* A0  : ESPI_IO0 ==> ESPI_IO_0 */
+	/* A1  : ESPI_IO1 ==> ESPI_IO_1 */
+	/* A2  : ESPI_IO2 ==> ESPI_IO_2 */
+	/* A3  : ESPI_IO3 ==> ESPI_IO_3 */
+	/* A4  : ESPI_CS# ==> ESPI_CS_L */
+	/* A5  : ESPI_ALERT0# ==> TP78 */
+	PAD_NC(GPP_A5, NONE),
+	/* A6  : ESPI_ALERT1# ==> TP88 */
+	PAD_NC(GPP_A6, NONE),
+	/* A7  : SRCCLK_OE7# ==> NC */
+	PAD_NC(GPP_A7, NONE),
+	/* A8  : SRCCLKREQ7# ==> CLKREQ_7 */
+	PAD_NC(GPP_A8, NONE),
+	/* A9  : ESPI_CLK ==> ESPI_CLK */
+	/* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */
+	/* A11 : PMC_I2C_SDA ==> NC */
+	PAD_NC(GPP_A11, NONE),
+	/* A12 : SATAXPCIE1 ==> CLKREQ_9B */
+	PAD_NC(GPP_A12, NONE),
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* A14 : USB_OC1# ==> USB_C1_OC_ODL */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	/* A15 : USB_OC2# ==> USB_C2_OC_ODL */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* A16 : USB_OC3# ==> USB_A0_OC_ODL */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	/* A17 : DISP_MISCC ==> NC */
+	PAD_NC(GPP_A17, NONE),
+	/* A18 : DDSP_HPDB ==> HDMI_HPD */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A19 : DDSP_HPD1 ==> USB_C2_AUX_DC_P */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF6),
+	/* A20 : DDSP_HPD2 ==> USB_C2_AUX_DC_N */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF6),
+	/* A21 : DDPC_CTRCLK ==> USB_C1_AUX_DC_P */
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
+	/* A22 : DDPC_CTRLDATA ==> USB_C1_AUX_DC_N */
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
+	/* A23 : ESPI_CS1# ==> AUD_HP_INT_L */
+	PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH),
+
+	/* B0  : SOC_VID0 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	/* B1  : SOC_VID1 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	/* B2  : VRALERT# ==> M2_SSD_PLA_L */
+	PAD_CFG_GPO(GPP_B2, 1, PLTRST),
+	/* B3  : PROC_GP2 ==> NC */
+	PAD_NC(GPP_B3, NONE),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* B5  : ISH_I2C0_SDA ==> NC */
+	PAD_NC(GPP_B5, NONE),
+	/* B6  : ISH_I2C0_SCL ==> NC */
+	PAD_NC(GPP_B6, NONE),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/* B9  : NC */
+	PAD_NC(GPP_B9, NONE),
+	/* B10 : NC */
+	PAD_NC(GPP_B10, NONE),
+	/* B11 : PMCALERT# ==> EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_B11, 1, DEEP),
+	/* B12 : SLP_S0# ==> SLP_S0_L */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* B13 : PLTRST# ==> PLT_RST_L */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* B14 : SPKR ==> GPP_B14_STRAP */
+	PAD_NC(GPP_B14, NONE),
+	/* B15 : TIME_SYNC0 ==> TP159 */
+	PAD_NC(GPP_B15, NONE),
+	/* B16 : I2C5_SDA ==> NC */
+	PAD_NC(GPP_B16, NONE),
+	/* B17 : I2C5_SCL ==> NC */
+	PAD_NC(GPP_B17, NONE),
+	/* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */
+	PAD_NC(GPP_B18, NONE),
+	/* B19 : NC */
+	PAD_NC(GPP_B19, NONE),
+	/* B20 : NC */
+	PAD_NC(GPP_B20, NONE),
+	/* B21 : NC */
+	PAD_NC(GPP_B21, NONE),
+	/* B22 : NC */
+	PAD_NC(GPP_B22, NONE),
+	/* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
+	PAD_NC(GPP_B23, NONE),
+
+	/* C0  : SMBCLK ==> DDR_SMB_CLK */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	/* C1  : SMBDATA ==> DDR_SMB_DATA */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	/* C2  : SMBALERT# ==> GPP_C2_STRAP */
+	PAD_NC(GPP_C2, NONE),
+	/* C3 : SML0CLK ==> USB_C0_AUX_DC_P */
+	PAD_NC(GPP_C3, NONE),
+	/* C4 : SML0DATA ==> USB_C0_AUX_DC_N */
+	PAD_NC(GPP_C4, NONE),
+	/* C5  : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */
+	PAD_NC(GPP_C5, NONE),
+	/* C6  : SML1CLK ==> NC */
+	PAD_NC(GPP_C6, NONE),
+	/* C7  : SML1DATA ==> NC */
+	PAD_NC(GPP_C7, NONE),
+
+	/* D0  : ISH_GP0 ==> PCH_FP_BOOT0 */
+	PAD_NC(GPP_D0, NONE),
+	/* D1  : ISH_GP1 ==> FP_RST_ODL */
+	PAD_CFG_GPO(GPP_D1, 1, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D3  : ISH_GP3 ==> EN_NFC_PWR */
+	PAD_CFG_GPO(GPP_D3, 1, DEEP),
+	/* D4  : IMGCLKOUT0 ==> BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_D4, 1, DEEP),
+	/* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* D6  : SRCCLKREQ1# ==> CLKREQ_1 */
+	PAD_NC(GPP_D6, NONE),
+	/* D7  : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	/* D8  : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	/* D9  : ISH_SPI_CS# ==> USB_C2_LSX_TX */
+	PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4),
+	/* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4),
+	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
+	/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
+	PAD_NC(GPP_D12, NONE),
+	/* D13 : ISH_UART0_RXD ==> TP97 */
+	PAD_NC(GPP_D13, NONE),
+	/* D14 : ISH_UART0_TXD ==> TP93 */
+	PAD_NC(GPP_D14, NONE),
+	/* D15 : ISH_UART0_RTS# ==> NC */
+	PAD_NC(GPP_D15, NONE),
+	/* D16 : ISH_UART0_CTS# ==> NC */
+	PAD_NC(GPP_D16, NONE),
+	/* D17 : UART1_RXD ==> SD_PE_PRSNT_L */
+	PAD_CFG_GPI(GPP_D17, NONE, DEEP),
+	/* D18 : UART1_TXD ==> SD_PE_RST_L */
+	PAD_CFG_GPO(GPP_D18, 1, DEEP),
+	/* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+
+	/* E0  : SATAXPCIE0 ==> CLKREQ_9 */
+	PAD_NC(GPP_E0, NONE),
+	/* E1  : THC0_SPI1_IO2 ==> NC */
+	PAD_NC(GPP_E1, NONE),
+	/* E2  : THC0_SPI1_IO3 ==> NC */
+	PAD_NC(GPP_E2, NONE),
+	/* E3  : PROC_GP0 ==> TP94644 */
+	PAD_NC(GPP_E3, NONE),
+	/* E4  : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_E4, 1, DEEP),
+	/* E5  : SATA_DEVSLP1 ==> NC */
+	PAD_NC(GPP_E5, NONE),
+	/* E6  : THC0_SPI1_RST# ==> GPPE6_STRAP */
+	PAD_NC(GPP_E6, NONE),
+	/* E7  : PROC_GP1 ==> TP94643 */
+	PAD_NC(GPP_E7, NONE),
+	/* E8  : SLP_DRAM# ==> WIFI_DISABLE_L */
+	PAD_CFG_GPO(GPP_E8, 1, DEEP),
+	/* E9  : USB_OC0# ==> USB_C0_OC_ODL */
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	/* E10 : THC0_SPI1_CS# ==> NC */
+	PAD_NC(GPP_E10, NONE),
+	/* E11 : THC0_SPI1_CLK ==> NC */
+	PAD_NC(GPP_E11, NONE),
+	/* E12 : THC0_SPI1_IO1 ==> NC */
+	PAD_NC(GPP_E12, NONE),
+	/* E13 : THC0_SPI1_IO2 ==> NC */
+	PAD_NC(GPP_E13, NONE),
+	/* E14 : DDSP_HPDA ==> SOC_DP_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* E16 : RSVD_TP ==> CLKREQ_8 */
+	PAD_NC(GPP_E16, NONE),
+	/* E17 : THC0_SPI1_INT# ==> TP102 */
+	PAD_NC(GPP_E17, NONE),
+	/* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_TX */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
+	/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_RX_STRAP */
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
+	/* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_TX */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
+	/* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_RX_STRAP */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
+	/* E22 : DDPA_CTRLCLK ==> DDIA_DP_CTRLCLK */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+	/* E23 : DDPA_CTRLDATA ==> DDIA_DP_CTRLDATA */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
+
+	/* F0  : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	/* F1  : CNV_BRI_RSP ==> CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+	/* F2  : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	/* F3  : CNV_RGI_RSP ==> CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+	/* F4  : CNV_RF_RESET# ==> CNV_RF_RST_L */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	/* F5  : MODEM_CLKREQ ==> CNV_CLKREQ0 */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
+	/* F6  : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+	/* F7  : GPPF7_STRAP */
+	PAD_NC(GPP_F7, NONE),
+	/* F8  : NC */
+	PAD_NC(GPP_F8, NONE),
+	/* F9  : BOOTMPC ==> SLP_S0_GATE_R */
+	PAD_CFG_GPO(GPP_F9, 1, PLTRST),
+	/* F10 : GPPF10_STRAP */
+	PAD_NC(GPP_F10, DN_20K),
+	/* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
+	/* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
+	/* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
+	/* F14 : GSXDIN ==> NC */
+	PAD_NC(GPP_F14, NONE),
+	/* F15 : GSXSRESET# ==> FPMCU_INT_L */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT),
+	/* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
+	/* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* F19 : SRCCLKREQ6# ==> LAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	/* F20 : EXT_PWR_GATE# ==> TP94669 */
+	PAD_NC(GPP_F20, NONE),
+	/* F21 : EXT_PWR_GATE2# ==> TP94579 */
+	PAD_NC(GPP_F21, NONE),
+	/* F22 : VNN_CTRL ==> TP153 */
+	PAD_NC(GPP_F22, NONE),
+	/* F23 : V1P05_CTRL ==> TP154 */
+	PAD_NC(GPP_F23, NONE),
+
+	/* H0  : GPPH0_BOOT_STRAP1 */
+	PAD_NC(GPP_H0, NONE),
+	/* H1  : GPPH1_BOOT_STRAP2 */
+	PAD_NC(GPP_H1, NONE),
+	/* H2  : GPPH2_BOOT_STRAP3 */
+	PAD_NC(GPP_H2, NONE),
+	/* H3  : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP),
+	/* H4  : I2C0_SDA ==> PCH_I2C_AUD_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> PCH_I2C_AUD_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H6  : I2C1_SDA ==> NC */
+	PAD_NC(GPP_H6, NONE),
+	/* H7  : I2C1_SCL ==> NC */
+	PAD_NC(GPP_H7, NONE),
+	/* H8  : I2C4_SDA ==> WWAN_WLAN_COEX1 */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
+	/* H9  : I2C4_SCL ==> WWAN_WLAN_COEX2 */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+	/* H14 : NC */
+	PAD_NC(GPP_H14, NONE),
+	/* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* H16 : NC */
+	PAD_NC(GPP_H16, NONE),
+	/* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	/* H19 : SRCCLKREQ4# ==> CLKREQ_4 */
+	PAD_NC(GPP_H19, NONE),
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 1, DEEP),
+	/* H21 : IMGCLKOUT2 ==>  TP94574 */
+	PAD_NC(GPP_H21, NONE),
+	/* H22 : IMGCLKOUT3 ==> LAN_PE_ISOLATE_ODL */
+	PAD_CFG_GPO(GPP_H22, 1, DEEP),
+	/* H23 : SRCCLKREQ5# ==> M2_SSD_PLN_L */
+	PAD_CFG_GPO(GPP_H23, 1, PLTRST),
+
+	/* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+	/* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+	/* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+	/* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+	/* R4 : HDA_RST# ==> DMIC_CLK0_R */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
+	/* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
+	/* R6 : I2S2_TXD ==> DMIC_CLK1_R */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
+	/* R7 : I2S2_RXD ==> DMIC_DATA1_R */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
+
+	/* S0 : SNDW0_CLK ==> NC */
+	PAD_NC(GPP_S0, NONE),
+	/* S1 : SNDW0_DATA ==> NC */
+	PAD_NC(GPP_S1, NONE),
+	/* S2 : SNDW1_CLK ==> NC */
+	PAD_NC(GPP_S2, NONE),
+	/* S3 : SNDW1_DATA ==> NC */
+	PAD_NC(GPP_S3, NONE),
+	/* S4 : SNDW2_CLK ==> NC */
+	PAD_NC(GPP_S4, NONE),
+	/* S5 : SNDW2_DATA ==> NC */
+	PAD_NC(GPP_S5, NONE),
+	/* S6 : SNDW3_CLK ==> NC */
+	PAD_NC(GPP_S6, NONE),
+	/* S7 : SNDW3_DATA ==> NC */
+	PAD_NC(GPP_S7, NONE),
+
+	/* GPD0: BATLOW# ==> BATLOW_L */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+	/* GPD1: ACPRESENT ==> ACPRESENT */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* GPD2 : LAN_WAKE# ==> EC_PCH_WAKE_ODL */
+	PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+	/* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */
+	PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+	/* GPD4: SLP_S3# ==> SLP_S3_L */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+	/* GPD5: SLP_S4# ==> SLP_S4_L */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+	/* GPD6: SLP_A# ==> SLP_A_L_CAP_SITE */
+	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+	/* GPD7: GPD7_STRAP */
+	PAD_NC(GPD7, NONE),
+	/* GPD8: SUSCLK ==> PCH_SUSCLK */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+	/* GPD9: SLP_WLAN# ==> SLP_WLAN_L_CAP_SITE */
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+	/* GPD10: SLP_S5# ==> SLP_S5_L */
+	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+	/* GPD11: LANPHYC ==> TP99 */
+	PAD_NC(GPD11, NONE),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+};
+
+const struct pad_config *__weak variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *__weak variant_gpio_override_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
+
+const struct pad_config *__weak variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
+{
+	*num = ARRAY_SIZE(cros_gpios);
+	return cros_gpios;
+}
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h
new file mode 100644
index 0000000000..43bf9513a6
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <baseboard/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+#define MAINBOARD_EC_SMI_EVENTS 0
+/* EC can wake from S5 with power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+/* EC can wake from S3 with power button */
+#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS)
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
+	(MAINBOARD_EC_S3_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+/*
+ * ACPI related definitions for ASL code.
+ */
+#define EC_ENABLE_WAKE_PIN      GPE_EC_WAKE
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+
+#define EC_ENABLE_SYNC_IRQ      /* Enable tight timestamp / wake support */
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/gpio.h
new file mode 100644
index 0000000000..0de7ffd36c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/gpio.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI		GPE0_ESPI
+/* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */
+#define GPE_EC_WAKE		GPE0_DW2_17
+/* WP signal to PCH */
+#define GPIO_PCH_WP		GPP_E15
+/* EC in RW or RO */
+#define GPIO_EC_IN_RW		GPP_F18
+/* Used to gate SoC's SLP_S0# signal */
+#define GPIO_SLP_S0_GATE	GPP_F9
+/* GPIO IRQ for tight timestamps / wake support */
+#define EC_SYNC_IRQ		GPP_F17_IRQ
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
index c938de820d..c938de820d 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/variants.h
+++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
diff --git a/src/mainboard/google/brya/variants/brask/include/variant/ec.h b/src/mainboard/google/brya/variants/brask/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brask/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/brya/variants/brask/include/variant/gpio.h b/src/mainboard/google/brya/variants/brask/include/variant/gpio.h
new file mode 100644
index 0000000000..27c87b3fe7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brask/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb
new file mode 100644
index 0000000000..4f2c04a57a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brask/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+        device domain 0 on
+        end
+
+end