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authorShelley Chen <shchen@google.com>2018-10-22 18:07:04 -0700
committerShelley Chen <shchen@google.com>2018-10-29 16:49:43 +0000
commitbf00401e8a4d58c2717ae0d9d45ea5a0114b0990 (patch)
tree0e47b40612ca4b79d09e6f9426530622eedeb00d /src/mainboard/google
parent6cc937e687d8761bcdf26a0b5a122c392238d10c (diff)
mb/google/poppy/variants/nami: Add field to identify single channel DDR
Variants of Nami need to accommodate single channel DDR. Will use GPP_D10 on nami for identification. GPP_D10 will return 1 when device is using single channel DDR and 0 when using dual channel DDR. BUG=b:117194353 BRANCH=None TEST=dmidecode | grep Channel and make sure that the correct number of channels gets returned. Change-Id: If86ab2c5404c4e818ce496ea935227ab5e51730a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/29233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/poppy/romstage.c5
-rw-r--r--src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h3
-rw-r--r--src/mainboard/google/poppy/variants/nami/gpio.c7
-rw-r--r--src/mainboard/google/poppy/variants/nami/memory.c4
4 files changed, 16 insertions, 3 deletions
diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c
index bac1e17889..9de1602a1a 100644
--- a/src/mainboard/google/poppy/romstage.c
+++ b/src/mainboard/google/poppy/romstage.c
@@ -171,7 +171,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
memcpy(&mem_cfg->RcompTarget, p.rcomp_target, p.rcomp_target_size);
mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(p.type, p.use_sec_spd);
- mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+ if (p.single_channel)
+ mem_cfg->MemorySpdPtr10 = 0;
+ else
+ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
mem_cfg->MemorySpdDataLen = spd_info[p.type].len;
mem_cfg->SaOcSupport = p.enable_sa_oc_support;
diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
index 31370aed2b..4c26d5e086 100644
--- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
@@ -60,6 +60,9 @@ struct memory_params {
/* The voltage offset applied to the SA in mV. 1000(mV) = Maximum */
uint16_t sa_voltage_offset_val;
+
+ /* This would be set to true if only have single DDR channel */
+ bool single_channel;
};
void variant_memory_params(struct memory_params *p);
diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c
index 1a03c05f7d..d74986a5c1 100644
--- a/src/mainboard/google/poppy/variants/nami/gpio.c
+++ b/src/mainboard/google/poppy/variants/nami/gpio.c
@@ -179,8 +179,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NC(GPP_D8),
/* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */
PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST),
- /* D10 : ISH_SPI_CLK ==> SPKR_RST_L (unstuffed) */
- PAD_CFG_NC(GPP_D10),
+ /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP),
/* D11 : ISH_SPI_MISO ==> DCI_CLK (debug header) */
PAD_CFG_NC(GPP_D11),
/* D12 : ISH_SPI_MOSI ==> DCI_DATA (debug header) */
@@ -370,6 +370,9 @@ static const struct pad_config early_gpio_table[] = {
/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
+
+ /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, 20K_PD, DEEP),
};
const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c
index 082b9a4417..b7f51851c7 100644
--- a/src/mainboard/google/poppy/variants/nami/memory.c
+++ b/src/mainboard/google/poppy/variants/nami/memory.c
@@ -89,4 +89,8 @@ void variant_memory_params(struct memory_params *p)
else
/* default to DDR4 */
fill_ddr4_memory_params(p);
+
+ /* GPP_D10 set to 0 for dual channel and 1 for single channel */
+ if (gpio_get(GPP_D10))
+ p->single_channel = 1;
}