diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-11-26 11:42:10 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-12-02 23:00:21 +0000 |
| commit | be104a2760044a91681d12e452ef3676f009a3a0 (patch) | |
| tree | b7c5d2a1766f7d724542f69ba26ac0b33162d4b6 /src/mainboard/google | |
| parent | b7eca6f123f8b04250b94380b5ac1c234a875728 (diff) | |
mb/google/brya: Add flashmap descriptor
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia1ba8c997680c60ee1eabfae82459e127f664117
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48062
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/Kconfig.name | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/chromeos.fmd | 49 |
2 files changed, 50 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index db2252afe3..2c0e513668 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -2,3 +2,4 @@ config BOARD_GOOGLE_BRYA0 bool "Brya 0" select BOARD_GOOGLE_BASEBOARD_BRYA select BASEBOARD_BRYA_LAPTOP + select BOARD_ROMSIZE_KB_32768 diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd new file mode 100644 index 0000000000..64776feee1 --- /dev/null +++ b/src/mainboard/google/brya/chromeos.fmd @@ -0,0 +1,49 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0x1b00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0xb00000 + RW_SECTION_A@0xb00000 0x5e0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x32ffc0 + RW_FWID_A@0x33ffc0 0x40 + ME_RW_A(CBFS)@0x340000 0x2a0000 + } + RW_SECTION_B@0x10e0000 0x5e0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x32ffc0 + RW_FWID_B@0x33ffc0 0x40 + ME_RW_B(CBFS)@0x340000 0x2a0000 + } + RW_MISC@0x16c0000 0x40000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x38000 0x2000 + RW_NVRAM(PRESERVE)@0x3a000 0x6000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x1700000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} |