diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-11-26 14:20:48 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-12-04 21:09:07 +0000 |
| commit | bca5bdb05661d5874d3c4b6de6a6f5a3fe5dc6cc (patch) | |
| tree | 1da62f3d99cacb30a3c364e76c8b038e4d47c28e /src/mainboard/google | |
| parent | e1d7d8464cb8503201bdcfb9dd02cb779e5a4417 (diff) | |
mb/google/brya: Enable ACPI and add ACPI table
Enable ACPI configuration and add DSDT ACPI table.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/dsdt.asl | 19 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 3c0875719f..e448e18e21 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SOC_INTEL_ALDERLAKE diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index 10d08e26e2..ebb6ec58f0 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -11,4 +11,23 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + /* Some generic macros */ + #include <soc/intel/common/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/common/acpi/sleepstates.asl> } |