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authorFurquan Shaikh <furquan@google.com>2018-10-23 08:03:06 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-10-25 09:22:53 +0000
commitb87ad06d2de5ce7c160362cfab0cd9d2d856c239 (patch)
treef5769239c12dccaf37c00e043b40d93738396519 /src/mainboard/google
parent156a63881f4294d320a8ceeac6c8d8fa1ef37566 (diff)
mb/google/fizz: Enable use of override devicetree
This change enables override device tree for Fizz to allow variants to provide their own overrides and also moves I2C5 realtek node to fizz/overridetree.cb since it doesn't apply to some variants being added for Fizz. Change-Id: Ia1a069fc539b51a22882ef94b55baf5bf7cd302f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/fizz/Kconfig4
-rw-r--r--src/mainboard/google/fizz/variants/baseboard/devicetree.cb10
-rw-r--r--src/mainboard/google/fizz/variants/fizz/overridetree.cb16
3 files changed, 21 insertions, 9 deletions
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 6ab94c910d..c82f8098ae 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -29,6 +29,10 @@ config DEVICETREE
string
default "variants/baseboard/devicetree.cb"
+config OVERRIDE_DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select VBOOT_EC_EFS
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 281d65ce87..ff0db37964 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -418,15 +418,7 @@ chip soc/intel/skylake
device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 on end # SATA
device pci 19.0 on end # UART #2
- device pci 19.1 on
- chip drivers/i2c/generic
- register "hid" = ""10EC5663""
- register "name" = ""RT53""
- register "desc" = ""Realtek RT5663""
- register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
- device i2c 13 on end
- end
- end # I2C #5
+ device pci 19.1 on end # I2C #5
device pci 19.2 off end # I2C #4
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
diff --git a/src/mainboard/google/fizz/variants/fizz/overridetree.cb b/src/mainboard/google/fizz/variants/fizz/overridetree.cb
new file mode 100644
index 0000000000..0d3c4fc54e
--- /dev/null
+++ b/src/mainboard/google/fizz/variants/fizz/overridetree.cb
@@ -0,0 +1,16 @@
+chip soc/intel/skylake
+
+ device domain 0 on
+ device pci 19.1 on
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5663""
+ register "name" = ""RT53""
+ register "desc" = ""Realtek RT5663""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
+ device i2c 13 on end
+ end
+ end # I2C #5
+
+ end
+
+end