diff options
| author | Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> | 2022-03-22 18:12:47 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-24 13:05:57 +0000 |
| commit | 9ffc9ebf250b57d22b06baa81e5a782ae95b72a1 (patch) | |
| tree | 86a3142d4a8b0ab57a437a1fa6bbbce347bc2a11 /src/mainboard/google | |
| parent | 79fe6a9537703458ff872e27ab9bc1d19c1380ea (diff) | |
mb/google/brya/baseboard/nissa: Enable DPTF for Nissa variants
BUG=b:224884901
BRANCH=None
TEST=Build FW and test on Nivviks board
Change-Id: I3f5e8dd3d2ff517e27b0b08a0173f094bc6043bd
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 2ce9a7d68d..9267e21557 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -22,6 +22,9 @@ chip soc/intel/alderlake # S0ix enable register "s0ix_enable" = "1" + # DPTF enable + register "dptf_enable" = "1" + # Enable CNVi BT register "cnvi_bt_core" = "true" |