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authorIonela Voinescu <ionela.voinescu@imgtec.com>2015-01-26 13:15:12 +0000
committerPatrick Georgi <pgeorgi@google.com>2015-04-14 12:08:23 +0200
commit8b1f23ef0307974737f49b237664f66f5e2c35c7 (patch)
tree29e27ae1b988b3f331bf0966a32c053b87fa5308 /src/mainboard/google
parent125427a07f7eec03d924f8cb3378bbe954804319 (diff)
urara: add clock setup for MIPS CPU, ROM and Ethernet
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works properly BRANCH=none Change-Id: Ie386d6af9eeba7a72b1b88d515e6cb1821569c6b Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d4b8d8b6f965296f9ecf62da8e5f383c3667b077 Original-Change-Id: I9eb464340b0475ae735ba5573ab0841dac0d74eb Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/243215 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9669 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/urara/bootblock.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c
index 6d90d5932e..b21a8885f4 100644
--- a/src/mainboard/google/urara/bootblock.c
+++ b/src/mainboard/google/urara/bootblock.c
@@ -110,13 +110,27 @@ static int init_clocks(void)
/* System PLL divided by 2 -> 400 MHz */
/* The same frequency will be the input frequency for the SPFI block */
system_clk_setup(1);
+
+ /* MIPS CPU dividers: division by 1 -> 550 MHz
+ * This is set up as we cannot make any assumption about
+ * the values set or not by the boot ROM code */
+ mips_clk_setup(0, 0);
+
/* System clock divided by 8 -> 50 MHz */
ret = usb_clk_setup(7, 2, 7);
if (ret != CLOCKS_OK)
return ret;
+
/* System PLL divided by 7 divided by 62 -> 1.8433 Mhz */
uart1_clk_setup(6, 61);
+ /* Ethernet clocks setup: ENET as clock source */
+ eth_clk_setup(0, 7);
+
+ /* ROM clock setup: system clock divided by 2 -> 200 MHz */
+ /* Hash accelerator is driven from the ROM clock */
+ rom_clk_setup(1);
+
/* Setup system PLL at 800 MHz */
ret = sys_pll_setup(2, 1);
if (ret != CLOCKS_OK)