diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-10-30 10:56:31 +0100 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-10 23:08:16 +0000 |
commit | 8084b3856852f3fb3905e0fe4957b08518095d38 (patch) | |
tree | c6aca7299eb82c0e6d5a2eba048a3373aa9fe9ca /src/mainboard/google | |
parent | b92df578b48911893a475b6f47ddfc574f63eac7 (diff) |
sb/intel/lynxpoint/sata: Always use AHCI mode
The other two modes are not used by any mainboard, and the code seems to
be copied from older southbridges. As the code looks incorrect, drop it.
Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r-- | src/mainboard/google/beltino/devicetree.cb | 2 | ||||
-rw-r--r-- | src/mainboard/google/slippy/devicetree.cb | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 8fdfbd79a0..176fced5ed 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -45,8 +45,6 @@ chip northbridge/intel/haswell register "gpe0_en_3" = "0x00000000" register "gpe0_en_4" = "0x00000000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sata_devslp_disable" = "0x1" diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 200721b8ef..a6fab83a5b 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -52,8 +52,6 @@ chip northbridge/intel/haswell register "gpe0_en_3" = "0x00000000" register "gpe0_en_4" = "0x00000000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sio_acpi_mode" = "1" |