diff options
| author | Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> | 2023-10-20 13:23:20 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-24 17:58:42 +0000 |
| commit | 731e28a938d583e39095fd553daadf84e5541ffe (patch) | |
| tree | 1a78adfa072a5aabbe89c77ddfa83aeb0d13ef90 /src/mainboard/google | |
| parent | ad1eec9df62f4a81d2562d2fbbb9992f4485c68e (diff) | |
mb/google/skyrim/var/crystaldrift: Update the STT settings
Adjust the STT settings.
BRANCH=none
BUG=b:270112575
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I1df9bbf820b5a760007dcfd7bceb21063fc24696
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78523
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb b/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb index 657fdb454b..d42dea7478 100644 --- a/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb @@ -22,10 +22,6 @@ end chip soc/amd/mendocino - # Set Package Power Parameters - # Remove the sustained_power_limit_mW when STT is enabled - register "sustained_power_limit_mW" = "15000" - device domain 0 on device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref xhci_1 on # XHCI1 controller @@ -131,4 +127,17 @@ chip soc/amd/mendocino end end end # I2C2 + + # Enable STT support + register "stt_control" = "1" + register "stt_pcb_sensor_count" = "2" + register "stt_min_limit" = "15000" + register "stt_m1" = "0x0555" + register "stt_m2" = "0xFDE4" + register "stt_c_apu" = "0x021A" + register "stt_alpha_apu" = "0x199A" + register "stt_skin_temp_apu" = "0x3000" + register "stt_error_coeff" = "0xA4" + register "stt_error_rate_coefficient" = "0x0E98" + end # chip soc/amd/mendocino |