diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-05-13 17:00:33 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-20 09:49:00 +0000 |
| commit | 6d20d0c1400a07b8ca3d709693263dbc45ca564f (patch) | |
| tree | e3940009f00f31d947ca0c12681effa5d911b8dd /src/mainboard/google | |
| parent | dbcf7b16219df0c04401b8fcd6a780174a7df305 (diff) | |
soc/intel/tigerlake: Move PMC PCI resources under PMC device
Historically in coreboot, the PMC's fixed PCI resources were described
by the System Agent (the MMIO resource), and eSPI/LPC (the I/O
resource). This patch moves both of those to a new Intel SoC-specific
function, soc_pmc_read_resources(). On TGL, this new function takes care
of providing the MMIO and I/O resources for the PMC.
BUG=b:156388055
TEST=verified on volteer that the resource allocator is aware of and
does not touch these two resources:
("PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0
flags f0000200 index 0
PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff
flags c0000100 index 1")
Also verify that the MEM resource is described in the coreboot table:
("BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved")
Verified the memory range is also untouchable from Linux:
("system 00:00: [mem 0xfe000000-0xffffffff] could not be reserved")
Change-Id: Ia7c6ae849aefaf549fb682416a87320907fb3fe3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41385
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 10 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 7350319b22..8d847f73fc 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -305,7 +305,7 @@ chip soc/intel/tigerlake end end # eSPI device pci 1f.1 off end # P2SB - device pci 1f.2 on end # PMC + device pci 1f.2 hidden end # PMC device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI Flash Controller diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index fa99de8c8f..5d5dcc4b70 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -370,7 +370,7 @@ chip soc/intel/tigerlake register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" device spi 0 on end end - end # GSPI0 0xA0AA + end # GSPI0 0xA0AA device pci 1e.3 on chip drivers/spi/acpi register "name" = ""CRFP"" @@ -380,14 +380,14 @@ chip soc/intel/tigerlake register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" device spi 0 on end end # FPMCU - end # GSPI1 0xA0AB + end # GSPI1 0xA0AB device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end end - end # eSPI 0xA080 - A09F + end # eSPI 0xA080 - A09F device pci 1f.1 off end # P2SB 0xA0A0 - device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.2 hidden end # PMC 0xA0A1 device pci 1f.3 on chip drivers/generic/max98357a register "hid" = ""MX98357A"" @@ -395,7 +395,7 @@ chip soc/intel/tigerlake register "sdmode_delay" = "5" device generic 0 on end end - end # Intel HD audio 0xA0C8-A0CF + end # Intel HD audio 0xA0C8-A0CF device pci 1f.4 off end # SMBus 0xA0A3 device pci 1f.5 on end # SPI 0xA0A4 device pci 1f.6 off end # GbE 0x15E1/0x15E2 |