diff options
| author | Tyler Wang <tyler.wang@quanta.corp-partner.google.com> | 2023-08-07 11:11:49 +0800 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-17 15:00:30 +0000 |
| commit | 6bdc000112837acdec777dfdc222747591ea58b5 (patch) | |
| tree | c2896f82b634646d3097e0ca8079d49388ae723b /src/mainboard/google | |
| parent | 3c4346fc8db30594ada075681536a8636c5d7292 (diff) | |
mb/google/rex/var/karis: Modify SSD settings
Follow schematic, modify SSD related settings.
BUG=b:294155897, b:289880020
TEST=emerge-rex coreboot
Change-Id: Ie9c228ed7ccc83afaa8365f89c1d5cdedc4f0c8c
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77006
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/rex/variants/karis/gpio.c | 8 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/karis/overridetree.cb | 12 |
2 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/rex/variants/karis/gpio.c b/src/mainboard/google/rex/variants/karis/gpio.c index 123fb364ae..4602983c5f 100644 --- a/src/mainboard/google/rex/variants/karis/gpio.c +++ b/src/mainboard/google/rex/variants/karis/gpio.c @@ -119,8 +119,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* GPP_C12 : [] ==> WWAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), - /* GPP_C13 : [] ==> SSD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* GPP_C13 : Not connected */ + PAD_NC(GPP_C13, NONE), /* GPP_C15 : [] ==> WWAN_DPR_SAR_ODL */ PAD_CFG_GPO(GPP_C15, 1, DEEP), /* GPP_C16 : [] ==> USB_C0_LSX_TX */ @@ -180,8 +180,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D18, NONE), /* GPP_D19 : [] ==> EC_SOC_REC_SWITCH_ODL */ PAD_CFG_GPI_LOCK(GPP_D19, NONE, LOCK_CONFIG), - /* GPP_D20 : net NC is not present in the given design */ - PAD_NC(GPP_D20, NONE), + /* GPP_D20 : [] ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* GPP_D21 : [] ==> WLAN_CLKREQ_ODLl */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), /* GPP_D22 : net NC is not present in the given design */ diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb index 793a46d7c5..080e2282bd 100644 --- a/src/mainboard/google/rex/variants/karis/overridetree.cb +++ b/src/mainboard/google/rex/variants/karis/overridetree.cb @@ -295,14 +295,14 @@ chip soc/intel/meteorlake device generic 0 alias dptf_policy on end end end - device ref pcie_rp9 on - # Enable SSD Card PCIE 9 using clk 4 - register "pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 4, - .clk_req = 4, + device ref pcie_rp10 on + # Enable SSD Card PCIE 10 using clk 8 + register "pcie_rp[PCIE_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - end #PCIE9 SSD card + end # PCIE10 SSD card device ref ish on probe ISH ISH_ENABLE chip drivers/intel/ish |