cpu/intel/sandybridge: Put stage cache into TSEG

TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.

The code is mostly copied from src/cpu/intel/haswell.

TESTED on Thinkpad X220: on a cold boot the stage cache gets created
and on S3 the cached ramstage gets properly used.

Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

0 files changed, 0 insertions, 0 deletions