diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2014-09-24 09:39:16 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2015-04-02 20:46:17 +0200 |
| commit | 5c2988c4616d8326f56037e7ef5e8280c134ef7d (patch) | |
| tree | 4b9d802bdb193e4ea12399ddec69e1b3965cbba5 /src/mainboard/google | |
| parent | 8d9a1bd5a84df71965488bfc49f07bdc1dcc1f9a (diff) | |
veyron: select rw romstage using vboot2
this change makes veyron pinky to select a rw romstage using vboot2.
BUG=None
TEST=Booted Veyron Pinky. Verified firmware selection in the log.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
CQ-DEPEND=CL:219100
Original-Change-Id: Ia1cfdacde9f8b17b00e7772a02e0d266afedb82f
Original-Reviewed-on: https://chromium-review.googlesource.com/219103
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 69c1e4b9ee200645d38d28165389aa85ef9b36cd)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7b4a2db8bcb95038dfb55bb7ceee66ac4a6c9475
Reviewed-on: http://review.coreboot.org/9234
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/veyron_pinky/Kconfig | 5 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_pinky/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_pinky/mainboard.c | 5 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_pinky/romstage.c | 10 |
4 files changed, 15 insertions, 7 deletions
diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index e2c9d1ae54..07b31fff16 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select MAINBOARD_HAS_BOOTBLOCK_INIT select HAVE_HARD_RESET + select RETURN_FROM_VERSTAGE config MAINBOARD_DIR string @@ -48,6 +49,10 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0 +config VBOOT_RAMSTAGE_INDEX + hex + default 0x3 + config BOOT_MEDIA_SPI_BUS int default 2 diff --git a/src/mainboard/google/veyron_pinky/Makefile.inc b/src/mainboard/google/veyron_pinky/Makefile.inc index 2d3f62f5b7..63fefe477e 100644 --- a/src/mainboard/google/veyron_pinky/Makefile.inc +++ b/src/mainboard/google/veyron_pinky/Makefile.inc @@ -17,8 +17,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## bootblock-y += bootblock.c +bootblock-y += chromeos.c bootblock-y += reset.c +verstage-y += chromeos.c verstage-y += reset.c romstage-y += romstage.c diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c index 4d647d3e09..0bbd496c64 100644 --- a/src/mainboard/google/veyron_pinky/mainboard.c +++ b/src/mainboard/google/veyron_pinky/mainboard.c @@ -57,13 +57,9 @@ static void setup_iomux(void) setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); - /*i2c1 for tpm*/ - writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); - /*i2c2 for codec*/ writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); - writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); writel(IOMUX_I2S, &rk3288_grf->iomux_i2s); writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk); writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc); @@ -127,7 +123,6 @@ static void mainboard_init(device_t dev) configure_sdmmc(); configure_emmc(); configure_i2s(); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); } static void mainboard_enable(device_t dev) diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index e1062ca9e9..31317a06a4 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -18,6 +18,7 @@ */ #include <types.h> +#include <arch/stages.h> #include <armv7.h> #include <cbfs.h> #include <console/console.h> @@ -68,8 +69,6 @@ void main(void) mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); dcache_mmu_enable(); - setup_chromeos_gpios(); - cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS @@ -79,5 +78,12 @@ void main(void) timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif + +#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) + void *entry = vboot_load_ramstage(); + if (entry != NULL) + stage_exit(entry); +#endif + run_ramstage(); } |