diff options
| author | Won Chung <wonchung@google.com> | 2022-05-23 23:04:30 +0000 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-05-28 04:52:32 +0000 |
| commit | 575b4e96e5df17b061998803c25d96ce8de831d2 (patch) | |
| tree | 5f82ea7a7f35462ce2b8fddd3bc927e6c23cd2dc /src/mainboard/google | |
| parent | 0d303393795e76281245309b68b49f8f459ce08e (diff) | |
mb/google/brya/var/taniks: Correct _PLD values
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
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| Screen |
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+----------------+
C0 | | C1
A | MLB DB | A
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ia66c6fafe08110b8d8f9a138a2516ae03f8e1809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/taniks/overridetree.cb | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index 6a10884cab..3877031e8f 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -410,7 +410,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on probe DB_USB DB_USB3_WITH_A end @@ -432,7 +432,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on probe DB_USB DB_USB3_WITH_A end @@ -447,7 +447,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-A Port (DB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port7 on probe DB_USB DB_USB3_WITH_A end @@ -456,7 +456,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -470,14 +470,14 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (DB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port3 on probe DB_USB DB_USB3_WITH_A end |