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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2016-05-27 09:05:02 +0200
committerMartin Roth <martinroth@google.com>2016-05-31 21:07:03 +0200
commit4acb0e774220c0705a71689b6620c976297d417c (patch)
tree1dfb1d5df4c4370739f3812088669293ddd80c39 /src/mainboard/google
parent0a54fb533d9b03ba4ad24bfc9180ee5803feef51 (diff)
commonlib/lz4: Avoid unaligned memory access on RISC-V
From the User-Level ISA Specification v2.0: "We do not mandate atomicity for misaligned accesses so simple implementations can just use a machine trap and software handler to handle misaligned accesses." (— http://riscv.org/specifications/) Spike traps on unaligned accesses. Change-Id: Ia57786916f4076cc08513f4e331c2deec9cfa785 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14983 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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