diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-12-13 09:26:39 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-19 06:24:43 +0000 |
| commit | 43825e89607db06ac96926ab9872887980fb2ad3 (patch) | |
| tree | 5d422960eaa31cb92b436d5aa0bef638bf6f2fbe /src/mainboard/google | |
| parent | 9bf1d8f2761d3f83123222225aab2673cde466a7 (diff) | |
mb/google/sarien: Enable DMI/SATA power Optimize
Turn on power optimizer of PCH side DMI and SATA controller.
BUG=N/A
TEST=Build and boot up into sarien platoform, able to finish 100 cycles
of s0ix.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I41da2b4106d683945cdc296e2a77311176144f43
Reviewed-on: https://review.coreboot.org/c/30212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index acdb623319..a8bb34233a 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -27,6 +27,8 @@ chip soc/intel/cannonlake register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" + register "dmipwroptimize" = "1" + register "satapwroptimize" = "1" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 2800ff588c..c24cd028e1 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -31,6 +31,8 @@ chip soc/intel/cannonlake register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" + register "dmipwroptimize" = "1" + register "satapwroptimize" = "1" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port |