diff options
| author | Nico Huber <nico.h@gmx.de> | 2024-01-12 16:22:19 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-19 13:19:26 +0000 |
| commit | 2bc4b934c35ca14ab1243c19dc6fa27688feefdb (patch) | |
| tree | 616e44e74f59f63376dbd7f3b5febbd31d02262c /src/mainboard/google | |
| parent | 3d80d14cd4ed82e74057cea884dcb9bb7588c076 (diff) | |
soc/intel/tigerlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
4 files changed, 16 insertions, 15 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 078deb29f2..fe13b77d5b 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -112,28 +112,24 @@ chip soc/intel/tigerlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - # Enable NVMe PCIE 9 using clk 0 - register "PcieRpEnable[8]" = "1" + # NVMe PCIE 9 using clk 0 register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" register "PcieRpSlotImplemented[8]" = "1" - # Enable Optane PCIE 11 using clk 0 - register "PcieRpEnable[10]" = "1" + # Optane PCIE 11 using clk 0 register "PcieRpLtrEnable[10]" = "1" register "HybridStorageMode" = "0" register "PcieRpSlotImplemented[10]" = "1" - # Enable SD Card PCIE 8 using clk 3 - register "PcieRpEnable[7]" = "1" + # SD Card PCIE 8 using clk 3 register "PcieRpLtrEnable[7]" = "1" register "PcieRpHotPlug[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" - # Enable WLAN PCIE 7 using clk 1 - register "PcieRpEnable[6]" = "1" + # WLAN PCIE 7 using clk 1 register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" @@ -469,7 +465,6 @@ chip soc/intel/tigerlake device ref i2c3 on end device ref heci1 on end device ref sata on end - device ref pcie_rp1 on end device ref pcie_rp7 on end device ref pcie_rp8 on probe DB_SD SD_GL9755S diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb index 28f72d70d6..53ed651bdd 100644 --- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb +++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb @@ -5,8 +5,7 @@ chip soc/intel/tigerlake register "DdiPort2Hpd" = "0" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" - # Enable EMMC PCIE 5 using clk 5 - register "PcieRpEnable[4]" = "1" + # EMMC PCIE 5 using clk 5 register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[5]" = "4" diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 2152ec479a..4adf76a882 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -5,8 +5,7 @@ chip soc/intel/tigerlake register "DdiPort2Hpd" = "0" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" - # Enable EMMC PCIE 5 using clk 5 - register "PcieRpEnable[4]" = "1" + # EMMC PCIE 5 using clk 5 register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[5]" = "4" diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index d101b5d34e..4c83c7e42d 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -12,13 +12,11 @@ chip soc/intel/tigerlake register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" # Disable WLAN PCIE 7 - register "PcieRpEnable[6]" = "0" register "PcieRpLtrEnable[6]" = "0" register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" register "PcieRpSlotImplemented[6]" = "1" # Disable SD Card PCIE 8 - register "PcieRpEnable[7]" = "0" register "PcieRpLtrEnable[7]" = "0" register "PcieRpHotPlug[7]" = "0" register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" @@ -102,6 +100,16 @@ chip soc/intel/tigerlake probe AUDIO MAX98360_ALC5682I_I2S probe AUDIO RT1011_ALC5682I_I2S end + device ref pcie_rp7 off end + device ref pcie_rp8 off + # override-devicetree rules say it's only + # the same device if it has the same probes: + probe DB_SD SD_GL9755S + probe DB_SD SD_RTS5261 + probe DB_SD SD_RTS5227S + probe DB_SD SD_GL9750 + probe DB_SD SD_OZ711LV2LN + end device ref pcie_rp9 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" |