diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2019-03-29 13:25:09 +0530 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-04-16 14:38:17 +0000 |
| commit | 250dfc025613f5e193183f9520432207f4b296e4 (patch) | |
| tree | de8dd8287be07f589b915d196aa5a7ee8a329cde /src/mainboard/google | |
| parent | a432f38e81cbc392562f80902808e7b27a73c10e (diff) | |
soc/intel/cannonlake: Configure Vmx support using Kconfig
Change VmxEnable UPD values based on Kconfig ENABLE_VMX
and remove it from Devicetree and chip.h
Remove Vmx dependency on Vt-d
Change-Id: I4180c2270038a28befd6ed53c9485905025a15ba
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32117
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 1507214f99..9ecbf00152 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -22,7 +22,6 @@ chip soc/intel/cannonlake register "SataPortsDevSlp[2]" = "1" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" - register "VmxEnable" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e4a92a96d5..625655b38c 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -26,7 +26,6 @@ chip soc/intel/cannonlake register "SataPortsDevSlp[2]" = "1" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" - register "VmxEnable" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s |