diff options
| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2022-02-25 09:36:45 +0800 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-03-29 15:41:43 +0000 |
| commit | 2183484e7aefdd576d01342ba4a7db74b480e8a3 (patch) | |
| tree | 0d9d09c6411582d835a22c469cd59eadf77d8652 /src/mainboard/google | |
| parent | acf16bf4f69e417c75021e49bd455a212adbcd46 (diff) | |
mb/google/cherry: Pre-initialize PCIe at the bootblock stage
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be
delayed 100ms (TPVPERL) for the power and clock to become stable.
Instead of asserting PERST# right before PCIe initialization and waiting
for 100ms, which is currently the only function of 'mtk_pcie_pre_init',
so that the extra 100ms delay in ramstage is avoided.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/cherry/bootblock.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c index c506cafc27..c811c4eb2e 100644 --- a/src/mainboard/google/cherry/bootblock.c +++ b/src/mainboard/google/cherry/bootblock.c @@ -5,6 +5,7 @@ #include <gpio.h> #include <soc/gpio.h> #include <soc/i2c.h> +#include <soc/pcie.h> #include <soc/spi.h> #include "gpio.h" @@ -43,6 +44,13 @@ static void usb3_hub_reset(void) void bootblock_mainboard_init(void) { + /* + * Initialize PCIe pinmux and assert PERST# early to reduce + * the impact of 100ms delay. + */ + if (CONFIG(PCI)) + mtk_pcie_pre_init(); + mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); nor_set_gpio_pinmux(); |