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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2024-01-16 15:36:46 +0530
committerSubrata Banik <subratabanik@google.com>2024-01-24 10:57:26 +0000
commit1b414d14fda03e7e579ed20c8a874b3a97c4b427 (patch)
tree6eddf5a8342415dea1b8a4125c391b54478abf1d /src/mainboard/google
parentc29035c1ea94db63c4687acf8baeac6013c4d500 (diff)
mb/google/rex/var/rex: Set TCC to 100°C
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature for rex. BUG=b:270664854 TEST=Build, boot and test on rex with value under sysfs /sys/bus/pci/devices/0000:00:04.0/tcc_offset_degree_celsius Change-Id: I9012984016ab3213102214025d6d8dc07c5d8974 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79992 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Peter Ou <peter.ou@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index 9f868406a1..58c1719b48 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -45,6 +45,9 @@ chip soc/intel/meteorlake
# DPTF enable
register "dptf_enable" = "1"
+ # Setting TCC of 100C = Tj max (110) - TCC_Offset (10)
+ register "tcc_offset" = "10"
+
# Enable CNVi BT
register "cnvi_bt_core" = "true"