diff options
| author | Felix Singer <felixsinger@posteo.net> | 2021-08-13 08:31:52 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-08-28 18:21:26 +0000 |
| commit | 0dcdb217cf4fe1d2e2055994930eda618e9fe892 (patch) | |
| tree | 7fe4277d10a93aa908cabdc591f1dfa40bca5b66 /src/mainboard/google | |
| parent | 621ae7c701033029352603f2978b7580295f59e3 (diff) | |
soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.
Also, add a release note for the upcoming 4.15 release.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/google')
19 files changed, 0 insertions, 41 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index eb85cb5323..d19f627393 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -83,14 +83,12 @@ chip soc/intel/alderlake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | #| I2C3 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | #+-------------------+---------------------------+ - register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 762aa84bbe..25b81ebc59 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -83,7 +83,6 @@ chip soc/intel/alderlake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio and WFC | #| I2C1 | Touchscreen | @@ -93,7 +92,6 @@ chip soc/intel/alderlake #| | for TPM communication | #| I2C5 | Trackpad | #+-------------------+---------------------------+ - register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 3a799944dd..857e4e144a 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -169,11 +169,9 @@ chip soc/intel/jasperlake register "tcc_offset" = "10" # TCC of 90C - # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required # format: # register "common_soc_config.<variable_name>" = "value" - register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT # VR config settings # Imon Slope correction specified in 1/100 increment values. Range is 0-200. diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 244598739b..72ed789aec 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -62,7 +62,6 @@ chip soc/intel/tigerlake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | Touchpad | #| I2C2 | ISH ? | @@ -70,7 +69,6 @@ chip soc/intel/tigerlake #| I2C5 | ISH ? | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, }, diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 90bd260207..561fe7cc4c 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -162,7 +162,6 @@ chip soc/intel/cannonlake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | Touchpad | #| I2C4 | H1 TPM | @@ -174,7 +173,6 @@ chip soc/intel/cannonlake register "common_soc_config.pch_thermal_trip" = "77" register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 180, diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 07b910049d..8ea6539bec 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -159,14 +159,12 @@ chip soc/intel/skylake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | Early TPM access | #| I2C2 | Touchpad | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST_PLUS, .rise_time_ns = 98, diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index d33c9fdf26..e79f7044fa 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -263,7 +263,6 @@ chip soc/intel/skylake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -272,7 +271,6 @@ chip soc/intel/skylake #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[0] = { .speed_mhz = 1, .early_init = 1, diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 3f7ce89f25..65e1014992 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -83,11 +83,6 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7d9d1e64ca..0535b5b492 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -195,11 +195,9 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" - # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required # format: # register "common_soc_config.<variable_name>" = "value" - register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 4319948b3a..62dd1f5099 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -158,7 +158,6 @@ chip soc/intel/skylake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -170,7 +169,6 @@ chip soc/intel/skylake #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 98, diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index c5d85390d5..249183b420 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -150,7 +150,6 @@ chip soc/intel/skylake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | H1 | #| I2C2 | Camera | @@ -160,7 +159,6 @@ chip soc/intel/skylake #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 885fcbd196..51da81aa94 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -191,7 +191,6 @@ chip soc/intel/skylake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -203,7 +202,6 @@ chip soc/intel/skylake #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[0] = { .speed_mhz = 1, .early_init = 1, diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 3c7930d7c4..098216d3c5 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -160,7 +160,6 @@ chip soc/intel/skylake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | @@ -173,7 +172,6 @@ chip soc/intel/skylake #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 2b7debdaf1..0d9c5bd033 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -166,7 +166,6 @@ chip soc/intel/skylake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -179,7 +178,6 @@ chip soc/intel/skylake #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 98, diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 4ea4740f87..b3812d704f 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -157,14 +157,12 @@ chip soc/intel/skylake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | Trackpad | #| I2C5 | Audio | #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index df571aacdd..b44e867b5b 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -150,7 +150,6 @@ chip soc/intel/skylake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | @@ -162,7 +161,6 @@ chip soc/intel/skylake #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 47709d9127..a73bb17427 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -151,7 +151,6 @@ chip soc/intel/cannonlake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | Touchpad | #| I2C4 | H1 TPM | @@ -163,7 +162,6 @@ chip soc/intel/cannonlake register "common_soc_config.pch_thermal_trip" = "77" register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 52, diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index f035b79119..f13a2af1fd 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -152,7 +152,6 @@ chip soc/intel/cannonlake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | Touchpad | #| I2C4 | H1 TPM | @@ -164,7 +163,6 @@ chip soc/intel/cannonlake register "common_soc_config.pch_thermal_trip" = "77" register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 100, diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ae81518eb6..dd24779cca 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -309,7 +309,6 @@ chip soc/intel/tigerlake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -321,7 +320,6 @@ chip soc/intel/tigerlake #| I2C3 | Camera, SAR1 | #| I2C5 | Trackpad | #+-------------------+---------------------------+ - register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, |