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authorTristan Shieh <tristan.shieh@mediatek.com>2018-10-19 17:29:23 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-05 13:35:59 +0000
commit0688ab8d95f18f718510cc17aeb01a47519a9a5a (patch)
tree05fcd7af442ef1f32e85b34d1cdf5ac25371d434 /src/mainboard/google
parent3a065f1a76feb4f23af6708caef5f912292610fd (diff)
google/kukui: Support TPM
Init SPI bus 0 to connect TPM, configure interrupt type of GPIO CR50_IRQ, implement tis_plat_irq_status(), and set up chromeos GPIO table for TPM interrupt. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui. Change-Id: Ieaa6ae65fbfb5ab6323e226e8171dd7a992c3a39 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/kukui/Kconfig7
-rw-r--r--src/mainboard/google/kukui/Makefile.inc1
-rw-r--r--src/mainboard/google/kukui/chromeos.c7
-rw-r--r--src/mainboard/google/kukui/gpio.h1
-rw-r--r--src/mainboard/google/kukui/verstage.c26
5 files changed, 41 insertions, 1 deletions
diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig
index 7032d674b8..5be904ceb6 100644
--- a/src/mainboard/google/kukui/Kconfig
+++ b/src/mainboard/google/kukui/Kconfig
@@ -2,7 +2,6 @@ if BOARD_GOOGLE_KUKUI
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
- select VBOOT_MOCK_SECDATA
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -15,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS
select SPI_FLASH_INCLUDE_ALL_DRIVERS
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_SPI
+ select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT
+ select MAINBOARD_HAS_TPM2 if VBOOT
config MAINBOARD_DIR
string
@@ -24,6 +25,10 @@ config MAINBOARD_PART_NUMBER
string
default "Kukui"
+config DRIVER_TPM_SPI_BUS
+ hex
+ default 0x0
+
config BOOT_DEVICE_SPI_FLASH_BUS
int
default 1
diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc
index a98541a35c..5fe073a590 100644
--- a/src/mainboard/google/kukui/Makefile.inc
+++ b/src/mainboard/google/kukui/Makefile.inc
@@ -5,6 +5,7 @@ bootblock-y += memlayout.ld
decompressor-y += memlayout.ld
verstage-y += chromeos.c
+verstage-y += verstage.c
verstage-y += memlayout.ld
romstage-y += boardid.c
diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c
index ace99bc11e..77c442f36a 100644
--- a/src/mainboard/google/kukui/chromeos.c
+++ b/src/mainboard/google/kukui/chromeos.c
@@ -16,6 +16,7 @@
#include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <gpio.h>
+#include <security/tpm/tis.h>
#include "gpio.h"
@@ -31,6 +32,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"},
{EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"},
+ {CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
@@ -39,3 +41,8 @@ int get_write_protect_state(void)
{
return 0;
}
+
+int tis_plat_irq_status(void)
+{
+ return gpio_eint_poll(CR50_IRQ);
+}
diff --git a/src/mainboard/google/kukui/gpio.h b/src/mainboard/google/kukui/gpio.h
index a2f77606ac..20a50a6923 100644
--- a/src/mainboard/google/kukui/gpio.h
+++ b/src/mainboard/google/kukui/gpio.h
@@ -20,6 +20,7 @@
#define EC_IRQ GPIO(PERIPHERAL_EN1)
#define EC_IN_RW GPIO(PERIPHERAL_EN14)
+#define CR50_IRQ GPIO(PERIPHERAL_EN3)
void setup_chromeos_gpios(void);
diff --git a/src/mainboard/google/kukui/verstage.c b/src/mainboard/google/kukui/verstage.c
new file mode 100644
index 0000000000..9bf93bf687
--- /dev/null
+++ b/src/mainboard/google/kukui/verstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <security/vboot/vboot_common.h>
+#include <soc/gpio.h>
+#include <soc/spi.h>
+
+#include "gpio.h"
+
+void verstage_mainboard_init(void)
+{
+ mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz);
+ gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
+}