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authorFelix Singer <felixsinger@posteo.net>2024-06-23 04:59:03 +0200
committerFelix Singer <felixsinger@posteo.net>2024-06-26 11:44:08 +0000
commitdf7de392ef5f8e1654df96a1a050820eb3779012 (patch)
tree341c3b10cc90f3831a9aadbb90d50d4edb0b47f4 /src/mainboard/google
parentdcddc53fde2d559beef998d3c17e9b7a227e3665 (diff)
skl mainboards/dt: Move SATA related settings into SATA device scope
Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/fizz/variants/baseboard/devicetree.cb11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 7d11653ff7..9458c81299 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -59,9 +59,6 @@ chip soc/intel/skylake
register "s0ix_enable" = true
# FSP Configuration
- register "SataPortsEnable[0]" = "1"
- register "SataPortsEnable[1]" = "1"
- register "SataPortsDevSlp[1]" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SkipExtGfxScan" = "1"
@@ -359,7 +356,13 @@ chip soc/intel/skylake
device ref i2c0 on end
device ref i2c2 on end
device ref heci1 on end
- device ref sata on end
+ device ref sata on
+ register "SataPortsEnable" = "{
+ [0] = 1,
+ [1] = 1,
+ }"
+ register "SataPortsDevSlp[1]" = "1"
+ end
device ref uart2 on end
device ref i2c5 on end
device ref pcie_rp1 on end