From df7de392ef5f8e1654df96a1a050820eb3779012 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 23 Jun 2024 04:59:03 +0200 Subject: skl mainboards/dt: Move SATA related settings into SATA device scope MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179 Reviewed-by: Eric Lai Reviewed-by: Erik van den Bogaert Reviewed-by: Marvin Evers Reviewed-by: Jonathon Hall Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 7d11653ff7..9458c81299 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -59,9 +59,6 @@ chip soc/intel/skylake register "s0ix_enable" = true # FSP Configuration - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[1]" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SkipExtGfxScan" = "1" @@ -359,7 +356,13 @@ chip soc/intel/skylake device ref i2c0 on end device ref i2c2 on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + }" + register "SataPortsDevSlp[1]" = "1" + end device ref uart2 on end device ref i2c5 on end device ref pcie_rp1 on end -- cgit v1.2.3