diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2023-06-26 09:45:42 +0530 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-06-28 16:26:38 +0000 |
| commit | b72ecf89639e66c57d39beb0d63ef8d0d8f396c8 (patch) | |
| tree | 3272438d40762f06c1324a00bf49a775758e0719 /src/mainboard/google | |
| parent | 24802076bf8ae9e4bd6bb88ff5fdd07a1965f822 (diff) | |
mb/google/rex: Set TCC to 90°C
Set tcc_offset value to 20 in devicetree for Thermal Control
Circuit (TCC) activation feature for rex variants.
BUG=b:270664854
BRANCH=None
TEST=Build FW and test on rex board
Change-Id: I0567b6240fcb53f38158c381b700169475cf3795
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76110
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 0d639e3731..7acc0ae047 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -36,6 +36,9 @@ chip soc/intel/meteorlake # DPTF enable register "dptf_enable" = "1" + # Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20) + register "tcc_offset" = "20" + # Enable CNVi BT register "cnvi_bt_core" = "true" |