From b72ecf89639e66c57d39beb0d63ef8d0d8f396c8 Mon Sep 17 00:00:00 2001
From: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Date: Mon, 26 Jun 2023 09:45:42 +0530
Subject: =?UTF-8?q?mb/google/rex:=20Set=20TCC=20to=2090=C2=B0C?=
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Set tcc_offset value to 20 in devicetree for Thermal Control
Circuit (TCC) activation feature for rex variants.

BUG=b:270664854
BRANCH=None
TEST=Build FW and test on rex board

Change-Id: I0567b6240fcb53f38158c381b700169475cf3795
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76110
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/mainboard/google')

diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index 0d639e3731..7acc0ae047 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -36,6 +36,9 @@ chip soc/intel/meteorlake
 	# DPTF enable
 	register "dptf_enable" = "1"
 
+	# Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20)
+	register "tcc_offset" = "20"
+
 	# Enable CNVi BT
 	register "cnvi_bt_core" = "true"
 
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