diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2019-01-29 10:47:54 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-31 08:43:01 +0000 |
| commit | 003fdcbda2fd1559b15e68ea1c5c23be8646ff2c (patch) | |
| tree | 436e9dd0863f8741d1480a0ce35fab0f66dc836b /src/mainboard/google | |
| parent | cd69259e0ce49713066882249ae11bd78c2494a6 (diff) | |
mb/google/sarien: Turn on ASPM L1.2 for Card Reader
Enable ASPM L1.2 support for embedded realtek card reader, after change
the power consumption for SD controller from 5mW to less than 2mW.
BUG=N/A
TEST=Build and boot up on Arcada platform, check the PCI configuration
on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader
is also 0x0f.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0
Reviewed-on: https://review.coreboot.org/c/31145
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4efaf55191..a47a53d4e0 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -100,6 +100,7 @@ chip soc/intel/cannonlake # PCIe port 11 for card reader register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 85d4f9def9..d3d26f9800 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -99,6 +99,7 @@ chip soc/intel/cannonlake # PCIe port 8 for Card Reader register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[4]" = "7" register "PcieClkSrcClkReq[4]" = "4" |