From 003fdcbda2fd1559b15e68ea1c5c23be8646ff2c Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 29 Jan 2019 10:47:54 -0800 Subject: mb/google/sarien: Turn on ASPM L1.2 for Card Reader Enable ASPM L1.2 support for embedded realtek card reader, after change the power consumption for SD controller from 5mW to less than 2mW. BUG=N/A TEST=Build and boot up on Arcada platform, check the PCI configuration on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader is also 0x0f. Signed-off-by: Lijian Zhao Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0 Reviewed-on: https://review.coreboot.org/c/31145 Reviewed-by: Duncan Laurie Reviewed-by: Roy Mingi Park Tested-by: build bot (Jenkins) --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 1 + src/mainboard/google/sarien/variants/sarien/devicetree.cb | 1 + 2 files changed, 2 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4efaf55191..a47a53d4e0 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -100,6 +100,7 @@ chip soc/intel/cannonlake # PCIe port 11 for card reader register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 85d4f9def9..d3d26f9800 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -99,6 +99,7 @@ chip soc/intel/cannonlake # PCIe port 8 for Card Reader register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[4]" = "7" register "PcieClkSrcClkReq[4]" = "4" -- cgit v1.2.3