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authorFelix Held <felix-coreboot@felixheld.de>2021-05-31 19:44:46 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-06-01 20:37:15 +0000
commit4fbab545b2a99407ff444a29730c443aee4f24db (patch)
treebd256e2e0a4f76cf7af09a55e17c33c3be4a646f /src/mainboard/google/zork/variants
parentc4eb45fa85d9860ce94829c6c977b9e28a297bf9 (diff)
mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard/google/zork/variants')
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb10
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb12
-rw-r--r--src/mainboard/google/zork/variants/vilboz/overridetree.cb8
3 files changed, 15 insertions, 15 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index 0d0e8299ca..57710c2b86 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -255,15 +255,15 @@ chip soc/amd/picasso
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
subsystemid 0x1022 0x1510 inherit
- device pci 0.2 on end # IOMMU
- device pci 1.2 on # GPP Bridge 1 - Wifi
+ device ref iommu on end
+ device ref gpp_bridge_1 on # Wifi
chip drivers/wifi/generic
register "wake" = "GEVENT_8"
device pci 00.0 on end
end
end
- device pci 1.3 on end # GPP Bridge 2 - SD
- device pci 8.1 on # Internal GPP Bridge 0 to Bus A
+ device ref gpp_bridge_2 on end # SD
+ device ref internal_bridge_a on
device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA
device pci 0.2 on end # Crypto Coprocessor
@@ -353,7 +353,7 @@ chip soc/amd/picasso
device pci 0.6 off end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
- device pci 14.3 on # - D14F3 bridge
+ device ref lpc_bridge on
chip ec/google/chromeec
device pnp 0c09.0 on
chip ec/google/chromeec/i2c_tunnel
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 8d0abad076..1ddc7632c7 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -248,16 +248,16 @@ chip soc/amd/picasso
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
subsystemid 0x1022 0x1510 inherit
- device pci 0.2 on end # IOMMU
- device pci 1.2 on # GPP Bridge 1 - Wifi
+ device ref iommu on end
+ device ref gpp_bridge_1 on # Wifi
chip drivers/wifi/generic
register "wake" = "GEVENT_8"
device pci 00.0 on end
end
end
- device pci 1.3 on end # GPP Bridge 2 - SD
- device pci 1.7 on end # GPP Bridge 6 - NVME
- device pci 8.1 on # Internal GPP Bridge 0 to Bus A
+ device ref gpp_bridge_2 on end # SD
+ device ref gpp_bridge_6 on end # NVME
+ device ref internal_bridge_a on
device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA
device pci 0.2 on end # Crypto Coprocessor
@@ -374,7 +374,7 @@ chip soc/amd/picasso
device pci 0.6 off end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
- device pci 14.3 on # - D14F3 bridge
+ device ref lpc_bridge on
chip ec/google/chromeec
device pnp 0c09.0 on
chip ec/google/chromeec/i2c_tunnel
diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
index 43a64b0d7e..7cadaf87c7 100644
--- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
@@ -152,13 +152,13 @@ chip soc/amd/picasso
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
subsystemid 0x1022 0x1510 inherit
- device pci 1.3 on
+ device ref gpp_bridge_2 on
chip drivers/generic/bayhub_lv2
register "enable_power_saving" = "1"
device pci 00.0 on end
end
- end # GPP Bridge 2 - SD
- device pci 8.1 on
+ end # SD
+ device ref internal_bridge_a on
device pci 0.5 on
chip drivers/amd/i2s_machine_dev
register "hid" = ""AMDI1015""
@@ -200,7 +200,7 @@ chip soc/amd/picasso
end
end # Audio
end
- device pci 14.3 on # - D14F3 bridge
+ device ref lpc_bridge on
chip ec/google/chromeec
device pnp 0c09.0 on
chip ec/google/chromeec/i2c_tunnel