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authorRaul E Rangel <rrangel@chromium.org>2020-05-20 14:07:41 -0600
committerMartin Roth <martinroth@google.com>2020-05-27 23:18:12 +0000
commitb3c41329fdca84a251c183bbc2b0767978e9d96f (patch)
tree47003eae89ad4f6dd86edb52b1fe203d7e7b14b5 /src/mainboard/google/zork/spd
parentfc9b8b916f7bc0c6ac1579b915937ed23ea3327a (diff)
mb/google/zork: Add Picasso based Zork mainboard and variants
This is a copy of the mb/google/zork directory from the chromiumos coreboot-zork branch. This was from commit 29308ac8606. See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork Changes: * Minor changes to make the board build. * Add bootblock.c. * Modify romstage.c * Removed the FSP_X configs from zork/Kconfig since they should be set in picasso/Kconfig. picasso/Kconfig doesn't currently define the binaries since they haven't been published. To get a working build a custom config that sets FSP_X_FILE is required. BUG=b:157140753 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/spd')
-rw-r--r--src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex32
-rw-r--r--src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex32
-rw-r--r--src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex32
-rw-r--r--src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex32
-rw-r--r--src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex32
-rw-r--r--src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex32
-rw-r--r--src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex32
-rw-r--r--src/mainboard/google/zork/spd/DDR4-template.spd.hex336
-rw-r--r--src/mainboard/google/zork/spd/Makefile.inc29
-rw-r--r--src/mainboard/google/zork/spd/empty.spd.hex33
-rw-r--r--src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex331
-rw-r--r--src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex33
-rw-r--r--src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex33
-rw-r--r--src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex33
-rw-r--r--src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex331
-rw-r--r--src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex331
-rw-r--r--src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex33
-rw-r--r--src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex33
-rw-r--r--src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex33
-rw-r--r--src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex33
-rw-r--r--src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex33
-rw-r--r--src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex33
-rw-r--r--src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex33
23 files changed, 1945 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex
new file mode 100644
index 0000000000..7ae89df525
--- /dev/null
+++ b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
+00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
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diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex
new file mode 100644
index 0000000000..8d9fd4d9bf
--- /dev/null
+++ b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00
+00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex
new file mode 100644
index 0000000000..af9ba32181
--- /dev/null
+++ b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 45 21 10 08 00 60 00 03 01 03 00 00
+00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
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diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex
new file mode 100644
index 0000000000..56677fa37a
--- /dev/null
+++ b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 85 21 10 08 00 60 00 03 01 03 00 00
+00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
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diff --git a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex
new file mode 100644
index 0000000000..cc1ca7384b
--- /dev/null
+++ b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 46 21 00 08 00 60 00 03 02 03 00 00
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diff --git a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex
new file mode 100644
index 0000000000..3b1a73e7b8
--- /dev/null
+++ b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
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diff --git a/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex
new file mode 100644
index 0000000000..07342ab8fc
--- /dev/null
+++ b/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
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diff --git a/src/mainboard/google/zork/spd/DDR4-template.spd.hex b/src/mainboard/google/zork/spd/DDR4-template.spd.hex
new file mode 100644
index 0000000000..6198f3daf1
--- /dev/null
+++ b/src/mainboard/google/zork/spd/DDR4-template.spd.hex
@@ -0,0 +1,336 @@
+# Generic DDR4 SPD template
+# Fields that are not required should be set to zero
+# CRC will be calculated when generating SPDs from this template, so no need
+# to update here
+
+# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512)
+23
+
+# SPD Revision (Rev. 1.1)
+11
+
+# Key Byte / DRAM Device Type (DDR4 SDRAM)
+0C
+
+# Key Byte / Module Type (nECC SO-DIMM)
+03
+
+# SDRAM Density and Banks (2BG/4BK/8Gb)
+45
+
+# SDRAM Addressing (16/10)
+21
+
+# Primary SDRAM Package Type (Flipchip SDP)
+00
+
+# SDRAM Optional Features (Unlimited MAC)
+08
+
+# SDRAM Thermal and Refresh Options (Reserved)
+00
+
+# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported)
+60
+
+# Secondary SDRAM Package Type
+00
+
+# Module Nominal Volatage, VDD (1.2V)
+03
+
+# Module Organization
+01
+
+# Module Memory Bus Width (LP/x64)
+03
+
+# Module Thermal Sensor (Termal sensor not incorporated)
+00
+
+# Extended Module Type (Reserved)
+00
+
+# Reserved
+00
+
+# Timebases (MTB : 125ps, FTB : 1ps)
+00
+
+# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns)
+06
+
+# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns)
+0D
+
+# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14)
+F8
+
+# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20)
+3F
+
+# CAS Latencies Supported, Third Byte
+00
+
+# CAS Latencies Supported, Fourth Byte
+00
+
+# Minimum CAS Latency Time (tAAmin) (13.75ns)
+6E
+
+# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns)
+6E
+
+# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns)
+6E
+
+# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns)
+11
+
+# tRASmin, Least Significant Byte (32ns)
+00
+
+# tRCmin, Least Significant Byte (45.75ns)
+6E
+
+# tRFC1min, LSB (350ns)
+F0
+
+# tRFC1min, MSB (350ns)
+0A
+
+# tRFC2min, LSB (260ns)
+20
+
+# tRFC2min, MSB (260ns)
+08
+
+# tRFC4min, LSB (160ns)
+00
+
+# tRFC4min, MSB (160ns)
+05
+
+# Upper Nibble for tFAW (30ns)
+00
+
+# tFAWmin LSB (30ns)
+F0
+
+# tRRD_Smin (5.3ns)
+2B
+
+# tRRD_L min (6.40ns)
+34
+
+# tCCD_Lmin, same bank group (5ns)
+28
+
+# tWRmin Upper Nibbles (15ns)
+00
+
+# tWRmin (15ns)
+78
+
+# tWTRmin Upper Nibbles (2.5ns/7.5ns)
+00
+
+# tWTR_Smin (2.5ns)
+14
+
+# tWTR_Lmin (7.5ns)
+3C
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+# Connector to SDRAM Bit Mapping (DQ0-3)
+00
+
+# Connector to SDRAM Bit Mapping (DQ4-7)
+00
+
+# Connector to SDRAM Bit Mapping (DQ8-11)
+00
+
+# Connector to SDRAM Bit Mapping (DQ12-15)
+00
+
+# Connector to SDRAM Bit Mapping (DQ16-19)
+00
+
+# Connector to SDRAM Bit Mapping (DQ20-23)
+00
+
+# Connector to SDRAM Bit Mapping (DQ24-27)
+00
+
+# Connector to SDRAM Bit Mapping (DQ28-31)
+00
+
+# Connector to SDRAM Bit Mapping (CB0-3)
+00
+
+# Connector to SDRAM Bit Mapping (CB4-7)
+00
+
+# Connector to SDRAM Bit Mapping (DQ32-35)
+00
+
+# Connector to SDRAM Bit Mapping (DQ36-39)
+00
+
+# Connector to SDRAM Bit Mapping (DQ40-43)
+00
+
+# Connector to SDRAM Bit Mapping (DQ44-47)
+00
+
+# Connector to SDRAM Bit Mapping (DQ48-51)
+00
+
+# Connector to SDRAM Bit Mapping (DQ52-55)
+00
+
+# Connector to SDRAM Bit Mapping (DQ56-59)
+00
+
+# Connector to SDRAM Bit Mapping (DQ60-63)
+00
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00
+
+# Fine offset for tCCD_Lmin, same bank group (5ns)
+00
+
+# tRRD_L min offset (6.40ns)
+9C
+
+# tRRD_Smin offset (blank)
+00
+
+# Fine offset for tRCmin (45.75ns)
+00
+
+# Fine offset for tRPmin (13.75ns)
+00
+
+# Fine offset for tRCDmin (13.75ns)
+00
+
+# Fine offset for tAAmin (13.75ns)
+00
+
+# Fine offset for tCKAVGmax (1.6ns)
+E7
+
+# Fine offset for tCKAVGmin (0.75ns)
+00
+
+# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte)
+00
+
+# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte)
+00
+
+# RC Extension, Module Nominal Height
+00
+
+# Module Maximum Thickness
+00
+
+# Reference Raw Card Used
+00
+
+# Address Mapping from Edge Connector to DRAM (Standard)
+00
+
+# Reserved
+00 00 00 00 00 00 00 00
+
+# Reserved (Must be coded as 0x00)
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00
+
+# CRC for Module Specific Section, LSB (CRC cover 128~253 byte)
+00
+
+# CRC for Module Specific Section, MSB (CRC cover 128~253 byte)
+00
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+# Module Manufacturer's ID Code, LSB (blank)
+00
+
+# Module Manufacturer's ID Code, MSB (blank)
+00
+
+# Module Manufacturing Location (blank)
+00
+
+# Module Manufacturing Date (Variable)
+00
+
+# Module Manufacturing Date (Variable)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Part Number (blank)
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00
+
+# Module Revision Code (Revision 0)
+00
+
+# DRAM Manufacturer's ID code, LSB (blank)
+00
+
+# DRAM Manufacturer's ID code, MSB (blank)
+00
+
+# DRAM Stepping (Undefined)
+00
+
+# Module Manufacturer's Specific Data (blank)
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00
+
+# Reserved
+00 00
+
+# End User Programmable
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/Makefile.inc b/src/mainboard/google/zork/spd/Makefile.inc
new file mode 100644
index 0000000000..e401fa6fdc
--- /dev/null
+++ b/src/mainboard/google/zork/spd/Makefile.inc
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This directory
+SPD_SOURCES_DIR := src/mainboard/$(MAINBOARDDIR)/spd
+
+# Ordered List of APCB entries, up to 16.
+# Entries should match this pattern {NAME}_x{1,2}
+# There should be a matching SPD hex file in SPD_SOURCES_DIR
+# matching the pattern {NAME}.spd.hex
+# The _x{1,2} suffix denotes single or dual channel
+# TODO: Remove channel suffix when b:141434940 is fixed
+# Alternatively, generated APCBs stored at
+# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included.
+APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x1 # 0b0000
+APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x2 # 0b0001
+APCB_SOURCES += empty # 0b0010
+APCB_SOURCES += empty # 0b0011
+APCB_SOURCES += empty # 0b0100
+APCB_SOURCES += empty # 0b0101
+APCB_SOURCES += empty # 0b0110
+APCB_SOURCES += empty # 0b0111
+APCB_SOURCES += empty # 0b1000
+APCB_SOURCES += empty # 0b1001
+APCB_SOURCES += empty # 0b1010
+APCB_SOURCES += empty # 0b1011
+APCB_SOURCES += empty # 0b1100
+APCB_SOURCES += empty # 0b1101
+APCB_SOURCES += empty # 0b1110
+APCB_SOURCES += empty # 0b1111
diff --git a/src/mainboard/google/zork/spd/empty.spd.hex b/src/mainboard/google/zork/spd/empty.spd.hex
new file mode 100644
index 0000000000..0d22dd0cf0
--- /dev/null
+++ b/src/mainboard/google/zork/spd/empty.spd.hex
@@ -0,0 +1,33 @@
+#Empty SPD - placeholder file
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex
new file mode 100644
index 0000000000..1c5e87f9d4
--- /dev/null
+++ b/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex
@@ -0,0 +1,331 @@
+# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512)
+23
+
+# SPD Revision (Rev. 1.1)
+11
+
+# Key Byte / DRAM Device Type (DDR4 SDRAM)
+0C
+
+# Key Byte / Module Type (nECC SO-DIMM)
+03
+
+# SDRAM Density and Banks (2BG/4BK/8Gb)
+45
+
+# SDRAM Addressing (16/10)
+21
+
+# Primary SDRAM Package Type (Flipchip SDP)
+00
+
+# SDRAM Optional Features (Unlimited MAC)
+08
+
+# SDRAM Thermal and Refresh Options (Reserved)
+00
+
+# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported)
+60
+
+# Secondary SDRAM Package Type
+00
+
+# Module Nominal Volatage, VDD (1.2V)
+03
+
+# Module Organization (1Rx16)
+02
+
+# Module Memory Bus Width (LP/x64)
+03
+
+# Module Thermal Sensor (Termal sensor not incorporated)
+00
+
+# Extended Module Type (Reserved)
+00
+
+# Reserved
+00
+
+# Timebases (MTB : 125ps, FTB : 1ps)
+00
+
+# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns)
+06
+
+# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns)
+0D
+
+# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14)
+F8
+
+# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20)
+3F
+
+# CAS Latencies Supported, Third Byte
+00
+
+# CAS Latencies Supported, Fourth Byte
+00
+
+# Minimum CAS Latency Time (tAAmin) (13.75ns)
+6E
+
+# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns)
+6E
+
+# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns)
+6E
+
+# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns)
+11
+
+# tRASmin, Least Significant Byte (32ns)
+00
+
+# tRCmin, Least Significant Byte (45.75ns)
+6E
+
+# tRFC1min, LSB (350ns)
+F0
+
+# tRFC1min, MSB (350ns)
+0A
+
+# tRFC2min, LSB (260ns)
+20
+
+# tRFC2min, MSB (260ns)
+08
+
+# tRFC4min, LSB (160ns)
+00
+
+# tRFC4min, MSB (160ns)
+05
+
+# Upper Nibble for tFAW (30ns)
+00
+
+# tFAWmin LSB (30ns)
+F0
+
+# tRRD_Smin (5.3ns)
+2B
+
+# tRRD_L min (6.40ns)
+34
+
+# tCCD_Lmin, same bank group (5ns)
+28
+
+# tWRmin Upper Nibbles (15ns)
+00
+
+# tWRmin (15ns)
+78
+
+# tWTRmin Upper Nibbles (2.5ns/7.5ns)
+00
+
+# tWTR_Smin (2.5ns)
+14
+
+# tWTR_Lmin (7.5ns)
+3C
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+# Connector to SDRAM Bit Mapping (DQ0-3)
+16
+
+# Connector to SDRAM Bit Mapping (DQ4-7)
+36
+
+# Connector to SDRAM Bit Mapping (DQ8-11)
+0B
+
+# Connector to SDRAM Bit Mapping (DQ12-15)
+35
+
+# Connector to SDRAM Bit Mapping (DQ16-19)
+16
+
+# Connector to SDRAM Bit Mapping (DQ20-23)
+36
+
+# Connector to SDRAM Bit Mapping (DQ24-27)
+0B
+
+# Connector to SDRAM Bit Mapping (DQ28-31)
+35
+
+# Connector to SDRAM Bit Mapping (CB0-3)
+00
+
+# Connector to SDRAM Bit Mapping (CB4-7)
+00
+
+# Connector to SDRAM Bit Mapping (DQ32-35)
+16
+
+# Connector to SDRAM Bit Mapping (DQ36-39)
+36
+
+# Connector to SDRAM Bit Mapping (DQ40-43)
+0B
+
+# Connector to SDRAM Bit Mapping (DQ44-47)
+35
+
+# Connector to SDRAM Bit Mapping (DQ48-51)
+16
+
+# Connector to SDRAM Bit Mapping (DQ52-55)
+36
+
+# Connector to SDRAM Bit Mapping (DQ56-59)
+0B
+
+# Connector to SDRAM Bit Mapping (DQ60-63)
+35
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00
+
+# Fine offset for tCCD_Lmin, same bank group (5ns)
+00
+
+# tRRD_L min offset (6.40ns)
+9C
+
+# tRRD_Smin offset (5.3ns)
+B5
+
+# Fine offset for tRCmin (45.75ns)
+00
+
+# Fine offset for tRPmin (13.75ns)
+00
+
+# Fine offset for tRCDmin (13.75ns)
+00
+
+# Fine offset for tAAmin (13.75ns)
+00
+
+# Fine offset for tCKAVGmax (1.6ns)
+E7
+
+# Fine offset for tCKAVGmin (0.75ns)
+00
+
+# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte)
+87
+
+# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte)
+2E
+
+# RC Extention, Module Nominal Height (30.00)
+0F
+
+# Module Maximum Thickness (1.0/1.2)
+01
+
+# Reference Raw Card Used (C0)
+02
+
+# Address Mapping from Edge Connector to DRAM (Standard)
+00
+
+# Reserved
+00 00 00 00 00 00 00 00
+
+# Reserved (Must be coded as 0x00)
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00
+
+# CRC for Module Specific Section, LSB (CRC cover 128~253 byte)
+C0
+
+# CRC for Module Specific Section, MSB (CRC cover 128~253 byte)
+E2
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+# Module Manufacturer's ID Code, LSB (SK hynix)
+80
+
+# Module Manufacturer's ID Code, MSB (SK hynix)
+AD
+
+# Module Manufacturing Location (SK hynix (Icheon))
+01
+
+# Module Manufacturing Date (Variable)
+00
+
+# Module Manufacturing Date (Variable)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Part Number (H5AN8G6NCJR-VKC )
+48 35 41 4E 38 47 36 4E 43 4A 52 2D 56 4B 43 20
+20 20 20 20
+
+# Module Revision Code (Revision 0)
+00
+
+# DRAM Manufacturer's ID code, LSB (SK hynix)
+80
+
+# DRAM Manufacturer's ID code, MSB (SK hynix)
+AD
+
+# DRAM Stepping (Undefined)
+FF
+
+# Module Manufacturer's Specific Data
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 DD
+
+# Reserved
+00 00
+
+# End User Programmable
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex
new file mode 100644
index 0000000000..144c8e3f08
--- /dev/null
+++ b/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex
@@ -0,0 +1,33 @@
+# Hynix H5AN8G6NDJR-XNC
+23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
+00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B4 00 00 00 00 E7 00 75 20
+0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 AD 01 00 00 00 00 00 00 48 35 41 4E 38 47 36
+4E 44 4A 52 2D 58 4E 43 20 20 20 20 20 00 80 AD
+FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex
new file mode 100644
index 0000000000..e75e4c12d9
--- /dev/null
+++ b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex
@@ -0,0 +1,33 @@
+# Hynix H5ANAG6NCMR-VKC
+23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00
+00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04
+16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 43 CE
+0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 AD 01 00 00 00 00 00 00 48 4D 41 41 31 47 53
+36 43 4D 52 38 4E 2D 56 4B 20 20 20 20 00 80 AD
+FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex
new file mode 100644
index 0000000000..3cfb32cfc8
--- /dev/null
+++ b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex
@@ -0,0 +1,33 @@
+# Hynix H5ANAG6NCMR-XNC
+23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00
+00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 A8 14 28 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 C0 6E
+0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 AD 01 00 00 00 00 00 00 48 35 41 4E 41 47 36
+4E 43 4D 52 2D 58 4E 43 20 20 20 20 20 00 80 AD
+FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex b/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex
new file mode 100644
index 0000000000..7ad9466cf4
--- /dev/null
+++ b/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex
@@ -0,0 +1,331 @@
+# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512)
+23
+
+# SPD Revision (Rev. 1.1)
+11
+
+# Key Byte / DRAM Device Type (DDR4 SDRAM)
+0C
+
+# Key Byte / Module Type (nECC SO-DIMM)
+03
+
+# SDRAM Density and Banks (2BG/4BK/8Gb)
+45
+
+# SDRAM Addressing (16/10)
+21
+
+# Primary SDRAM Package Type (Flipchip SDP)
+00
+
+# SDRAM Optional Features (Unlimited MAC)
+08
+
+# SDRAM Thermal and Refresh Options (Reserved)
+00
+
+# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported)
+60
+
+# Secondary SDRAM Package Type
+00
+
+# Module Nominal Volatage, VDD (1.2V)
+03
+
+# Module Organization (1Rx16)
+02
+
+# Module Memory Bus Width (LP/x64)
+03
+
+# Module Thermal Sensor (Termal sensor not incorporated)
+00
+
+# Extended Module Type (Reserved)
+00
+
+# Reserved
+00
+
+# Timebases (MTB : 125ps, FTB : 1ps)
+00
+
+# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns)
+06
+
+# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns)
+0D
+
+# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14)
+F8
+
+# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20)
+3F
+
+# CAS Latencies Supported, Third Byte
+00
+
+# CAS Latencies Supported, Fourth Byte
+00
+
+# Minimum CAS Latency Time (tAAmin) (13.75ns)
+6E
+
+# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns)
+6E
+
+# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns)
+6E
+
+# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns)
+11
+
+# tRASmin, Least Significant Byte (32ns)
+00
+
+# tRCmin, Least Significant Byte (45.75ns)
+6E
+
+# tRFC1min, LSB (350ns)
+F0
+
+# tRFC1min, MSB (350ns)
+0A
+
+# tRFC2min, LSB (260ns)
+20
+
+# tRFC2min, MSB (260ns)
+08
+
+# tRFC4min, LSB (160ns)
+00
+
+# tRFC4min, MSB (160ns)
+05
+
+# Upper Nibble for tFAW (30ns)
+00
+
+# tFAWmin LSB (30ns)
+F0
+
+# tRRD_Smin (5.3ns)
+2B
+
+# tRRD_L min (6.40ns)
+34
+
+# tCCD_Lmin, same bank group (5ns)
+28
+
+# tWRmin Upper Nibbles (15ns)
+00
+
+# tWRmin (15ns)
+78
+
+# tWTRmin Upper Nibbles (2.5ns/7.5ns)
+00
+
+# tWTR_Smin (2.5ns)
+14
+
+# tWTR_Lmin (7.5ns)
+3C
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+# Connector to SDRAM Bit Mapping (DQ0-3)
+16
+
+# Connector to SDRAM Bit Mapping (DQ4-7)
+36
+
+# Connector to SDRAM Bit Mapping (DQ8-11)
+0B
+
+# Connector to SDRAM Bit Mapping (DQ12-15)
+35
+
+# Connector to SDRAM Bit Mapping (DQ16-19)
+16
+
+# Connector to SDRAM Bit Mapping (DQ20-23)
+36
+
+# Connector to SDRAM Bit Mapping (DQ24-27)
+0B
+
+# Connector to SDRAM Bit Mapping (DQ28-31)
+35
+
+# Connector to SDRAM Bit Mapping (CB0-3)
+00
+
+# Connector to SDRAM Bit Mapping (CB4-7)
+00
+
+# Connector to SDRAM Bit Mapping (DQ32-35)
+16
+
+# Connector to SDRAM Bit Mapping (DQ36-39)
+36
+
+# Connector to SDRAM Bit Mapping (DQ40-43)
+0B
+
+# Connector to SDRAM Bit Mapping (DQ44-47)
+35
+
+# Connector to SDRAM Bit Mapping (DQ48-51)
+16
+
+# Connector to SDRAM Bit Mapping (DQ52-55)
+36
+
+# Connector to SDRAM Bit Mapping (DQ56-59)
+0B
+
+# Connector to SDRAM Bit Mapping (DQ60-63)
+35
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00
+
+# Fine offset for tCCD_Lmin, same bank group (5ns)
+00
+
+# tRRD_L min offset (6.40ns)
+9C
+
+# tRRD_Smin offset (5.3ns)
+B5
+
+# Fine offset for tRCmin (45.75ns)
+00
+
+# Fine offset for tRPmin (13.75ns)
+00
+
+# Fine offset for tRCDmin (13.75ns)
+00
+
+# Fine offset for tAAmin (13.75ns)
+00
+
+# Fine offset for tCKAVGmax (1.6ns)
+E7
+
+# Fine offset for tCKAVGmin (0.75ns)
+00
+
+# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte)
+87
+
+# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte)
+2E
+
+# RC Extention, Module Nominal Height (30.00)
+0F
+
+# Module Maximum Thickness (1.0/1.2)
+01
+
+# Reference Raw Card Used (C0)
+02
+
+# Address Mapping from Edge Connector to DRAM (Standard)
+00
+
+# Reserved
+00 00 00 00 00 00 00 00
+
+# Reserved (Must be coded as 0x00)
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00
+
+# CRC for Module Specific Section, LSB (CRC cover 128~253 byte)
+C0
+
+# CRC for Module Specific Section, MSB (CRC cover 128~253 byte)
+E2
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+# Module Manufacturer's ID Code, LSB (SK hynix)
+80
+
+# Module Manufacturer's ID Code, MSB (SK hynix)
+AD
+
+# Module Manufacturing Location (SK hynix (Icheon))
+01
+
+# Module Manufacturing Date (Variable)
+00
+
+# Module Manufacturing Date (Variable)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Part Number (HMA851S6CJR6N-VK )
+48 4D 41 38 35 31 53 36 43 4A 52 36 4E 2D 56 4B
+20 20 20 20
+
+# Module Revision Code (Revision 0)
+00
+
+# DRAM Manufacturer's ID code, LSB (SK hynix)
+80
+
+# DRAM Manufacturer's ID code, MSB (SK hynix)
+AD
+
+# DRAM Stepping (Undefined)
+FF
+
+# Module Manufacturer's Specific Data
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 DD
+
+# Reserved
+00 00
+
+# End User Programmable
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex b/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex
new file mode 100644
index 0000000000..ff166d6e75
--- /dev/null
+++ b/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex
@@ -0,0 +1,331 @@
+# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512)
+23
+
+# SPD Revision (Rev. 1.1)
+11
+
+# Key Byte / DRAM Device Type (DDR4 SDRAM)
+0C
+
+# Key Byte / Module Type (nECC SO-DIMM)
+03
+
+# SDRAM Density and Banks (2BG/4BK/8Gb)
+45
+
+# SDRAM Addressing (16/10)
+21
+
+# Primary SDRAM Package Type (DDP)
+91
+
+# SDRAM Optional Features (Unlimited MAC)
+08
+
+# SDRAM Thermal and Refresh Options (Reserved)
+00
+
+# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported)
+60
+
+# Secondary SDRAM Package Type
+00
+
+# Module Nominal Volatage, VDD (1.2V)
+03
+
+# Module Organization (1Rx8)
+01
+
+# Module Memory Bus Width (LP/x64)
+03
+
+# Module Thermal Sensor (Termal sensor not incorporated)
+00
+
+# Extended Module Type (Reserved)
+00
+
+# Reserved
+00
+
+# Timebases (MTB : 125ps, FTB : 1ps)
+00
+
+# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns)
+06
+
+# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns)
+0D
+
+# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14)
+F8
+
+# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20)
+3F
+
+# CAS Latencies Supported, Third Byte
+00
+
+# CAS Latencies Supported, Fourth Byte
+00
+
+# Minimum CAS Latency Time (tAAmin) (13.75ns)
+6E
+
+# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns)
+6E
+
+# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns)
+6E
+
+# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns)
+11
+
+# tRASmin, Least Significant Byte (32ns)
+00
+
+# tRCmin, Least Significant Byte (45.75ns)
+6E
+
+# tRFC1min, LSB (350ns)
+F0
+
+# tRFC1min, MSB (350ns)
+0A
+
+# tRFC2min, LSB (260ns)
+20
+
+# tRFC2min, MSB (260ns)
+08
+
+# tRFC4min, LSB (160ns)
+00
+
+# tRFC4min, MSB (160ns)
+05
+
+# Upper Nibble for tFAW (30ns)
+00
+
+# tFAWmin LSB (30ns)
+F0
+
+# tRRD_Smin (5.3ns)
+2B
+
+# tRRD_L min (6.40ns)
+34
+
+# tCCD_Lmin, same bank group (5ns)
+28
+
+# tWRmin Upper Nibbles (15ns)
+00
+
+# tWRmin (15ns)
+78
+
+# tWTRmin Upper Nibbles (2.5ns/7.5ns)
+00
+
+# tWTR_Smin (2.5ns)
+14
+
+# tWTR_Lmin (7.5ns)
+3C
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+# Connector to SDRAM Bit Mapping (DQ0-3)
+16
+
+# Connector to SDRAM Bit Mapping (DQ4-7)
+36
+
+# Connector to SDRAM Bit Mapping (DQ8-11)
+0B
+
+# Connector to SDRAM Bit Mapping (DQ12-15)
+35
+
+# Connector to SDRAM Bit Mapping (DQ16-19)
+16
+
+# Connector to SDRAM Bit Mapping (DQ20-23)
+36
+
+# Connector to SDRAM Bit Mapping (DQ24-27)
+0B
+
+# Connector to SDRAM Bit Mapping (DQ28-31)
+35
+
+# Connector to SDRAM Bit Mapping (CB0-3)
+00
+
+# Connector to SDRAM Bit Mapping (CB4-7)
+00
+
+# Connector to SDRAM Bit Mapping (DQ32-35)
+16
+
+# Connector to SDRAM Bit Mapping (DQ36-39)
+36
+
+# Connector to SDRAM Bit Mapping (DQ40-43)
+0B
+
+# Connector to SDRAM Bit Mapping (DQ44-47)
+35
+
+# Connector to SDRAM Bit Mapping (DQ48-51)
+16
+
+# Connector to SDRAM Bit Mapping (DQ52-55)
+36
+
+# Connector to SDRAM Bit Mapping (DQ56-59)
+0B
+
+# Connector to SDRAM Bit Mapping (DQ60-63)
+35
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00
+
+# Fine offset for tCCD_Lmin, same bank group (5ns)
+00
+
+# tRRD_L min offset (6.40ns)
+9C
+
+# tRRD_Smin offset (5.3ns)
+B5
+
+# Fine offset for tRCmin (45.75ns)
+00
+
+# Fine offset for tRPmin (13.75ns)
+00
+
+# Fine offset for tRCDmin (13.75ns)
+00
+
+# Fine offset for tAAmin (13.75ns)
+00
+
+# Fine offset for tCKAVGmax (1.6ns)
+E7
+
+# Fine offset for tCKAVGmin (0.75ns)
+00
+
+# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte)
+FD
+
+# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte)
+EE
+
+# RC Extention, Module Nominal Height (30.00)
+0F
+
+# Module Maximum Thickness (1.0/1.2)
+01
+
+# Reference Raw Card Used (ZZ0)
+1F
+
+# Address Mapping from Edge Connector to DRAM (Standard)
+00
+
+# Reserved
+00 00 00 00 00 00 00 00
+
+# Reserved (Must be coded as 0x00)
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00
+
+# CRC for Module Specific Section, LSB (CRC cover 128~253 byte)
+7D
+
+# CRC for Module Specific Section, MSB (CRC cover 128~253 byte)
+21
+
+# Reserved
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+# Module Manufacturer's ID Code, LSB (SK hynix)
+80
+
+# Module Manufacturer's ID Code, MSB (SK hynix)
+AD
+
+# Module Manufacturing Location (SK hynix (Icheon))
+01
+
+# Module Manufacturing Date (Variable)
+00
+
+# Module Manufacturing Date (Variable)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Serial Number (Undefined)
+00
+
+# Module Part Number (HMAA1GS6CMR6N-VK )
+48 4D 41 41 31 47 53 36 43 4D 52 36 4E 2D 56 4B
+20 20 20 20
+
+# Module Revision Code (Revision 0)
+00
+
+# DRAM Manufacturer's ID code, LSB (SK hynix)
+80
+
+# DRAM Manufacturer's ID code, MSB (SK hynix)
+AD
+
+# DRAM Stepping (Undefined)
+FF
+
+# Module Manufacturer's Specific Data
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 DD
+
+# Reserved
+00 00
+
+# End User Programmable
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex
new file mode 100644
index 0000000000..17778473af
--- /dev/null
+++ b/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex
@@ -0,0 +1,33 @@
+# Micron MT40A1G16KD-062E:E
+23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
+00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 7C A0
+0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47
+31 36 4B 44 2D 30 36 32 45 3A 45 20 20 31 80 2C
+45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex
new file mode 100644
index 0000000000..988ea54b23
--- /dev/null
+++ b/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex
@@ -0,0 +1,33 @@
+# Micron MT40A1G16KNR-075:E
+23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00
+00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 8D 60
+0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47
+31 36 4B 4E 52 2D 30 37 35 3A 45 20 20 31 80 2C
+45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex
new file mode 100644
index 0000000000..67640fe849
--- /dev/null
+++ b/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex
@@ -0,0 +1,33 @@
+# MT40A512M16TB-062E:J
+23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
+00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 30 53
+0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 35 31
+32 4D 31 36 54 42 2D 30 36 32 45 3A 4A 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex
new file mode 100644
index 0000000000..e16d2f729b
--- /dev/null
+++ b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex
@@ -0,0 +1,33 @@
+# Samsung K4A8G165WC-BCTD
+23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
+00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 87 2e
+0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36
+35 57 43 2D 42 43 54 44 20 20 20 20 20 00 80 CE
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex
new file mode 100644
index 0000000000..4fb1561c6a
--- /dev/null
+++ b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex
@@ -0,0 +1,33 @@
+# Samsung K4A8G165WC-BCWE
+23 11 0C 03 46 21 00 08 00 60 00 03 02 03 00 00
+00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 14 98
+0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36
+35 57 43 2D 42 43 57 45 20 20 20 20 20 00 80 CE
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex b/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex
new file mode 100644
index 0000000000..390e5a5417
--- /dev/null
+++ b/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex
@@ -0,0 +1,33 @@
+# Samsung K4AAG165WA-BCWE
+23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
+00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5
+0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36
+35 57 41 2D 42 43 57 45 20 20 20 20 20 00 80 CE
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex b/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex
new file mode 100644
index 0000000000..ede001a4d5
--- /dev/null
+++ b/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex
@@ -0,0 +1,33 @@
+# Samsung K4AAG165WB-MCTD
+23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00
+00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04
+16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 D0 4E
+0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 4B
+34 33 42 42 31 2D 43 54 44 20 20 20 20 00 80 CE
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00