diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2020-05-20 14:07:41 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2020-05-27 23:18:12 +0000 |
| commit | b3c41329fdca84a251c183bbc2b0767978e9d96f (patch) | |
| tree | 47003eae89ad4f6dd86edb52b1fe203d7e7b14b5 /src/mainboard/google/zork/chromeos.fmd | |
| parent | fc9b8b916f7bc0c6ac1579b915937ed23ea3327a (diff) | |
mb/google/zork: Add Picasso based Zork mainboard and variants
This is a copy of the mb/google/zork directory from the chromiumos
coreboot-zork branch. This was from commit 29308ac8606.
See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork
Changes:
* Minor changes to make the board build.
* Add bootblock.c.
* Modify romstage.c
* Removed the FSP_X configs from zork/Kconfig since they should be
set in picasso/Kconfig. picasso/Kconfig doesn't currently define the
binaries since they haven't been published. To get a working build
a custom config that sets FSP_X_FILE is required.
BUG=b:157140753
TEST=Build trembyle and boot to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/chromeos.fmd')
| -rw-r--r-- | src/mainboard/google/zork/chromeos.fmd | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd new file mode 100644 index 0000000000..963d1ee841 --- /dev/null +++ b/src/mainboard/google/zork/chromeos.fmd @@ -0,0 +1,38 @@ +FLASH@0xFF000000 0x1000000 { + SI_BIOS@0x0 0x1000000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RW_MRC_CACHE@0x0 0x10000 + MRC_CACHE_HOLE@0x10000 0x11000 + } + RW_SECTION_A@0x21000 0x39E000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x38DFC0 + RW_FWID_A@0x39DFC0 0x40 + } + RW_SECTION_B@0x3BF000 0x39E000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x38DFC0 + RW_FWID_B@0x39DFC0 0x40 + } + RW_ELOG(PRESERVE)@0x75D000 0x4000 + RW_SHARED@0x761000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x765000 0x2000 + RW_NVRAM(PRESERVE)@0x767000 0x5000 + RW_UNUSED@0x76C000 0x14000 + SMMSTORE(PRESERVE)@0x780000 0x20000 + RW_LEGACY(CBFS)@0x7A0000 0x360000 + WP_RO@0xB00000 0x500000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x4FC000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7C0 + GBB@0x1000 0x70000 + COREBOOT(CBFS)@0x71000 0x48B000 + } + } + } +} |