diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2018-01-16 08:22:45 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-01-22 13:26:52 +0000 |
| commit | 9d1eb292c355a7fdfdb09ce8ccf2eeeae5f846d4 (patch) | |
| tree | 1c5b145bef5b8a026add9e145ea7b67a94d0f8ad /src/mainboard/google/zoombini/variants | |
| parent | f5c416c044b8f1538aea6c677b67412cbb96d784 (diff) | |
mainboard/google/zoombini/variants/meowth: enable PCH_FP_PWR_EN
Turn on the load switch to the FP MCU at startup, so the kernel can
detect it and use it.
The load switch enable pin is connected to the GPP_A11 PCH pin (aka
PCH_FP_PWR_EN).
BRANCH=none
BUG=b:71986991
TEST=on Meowth, see the kernel detecting a cros_fp device at startup:
[ 2.133456] cros-ec-spi spi-PRP0001:00: Fingerprint MCU detected.
[ 2.157420] cros-ec-spi spi-PRP0001:00: Chrome EC device registered
Change-Id: Id3c40b965a5f018c63481c2e2eea3fc8307352bd
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/zoombini/variants')
| -rw-r--r-- | src/mainboard/google/zoombini/variants/meowth/gpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/zoombini/variants/meowth/gpio.c b/src/mainboard/google/zoombini/variants/meowth/gpio.c index f4ae9b827a..790567f150 100644 --- a/src/mainboard/google/zoombini/variants/meowth/gpio.c +++ b/src/mainboard/google/zoombini/variants/meowth/gpio.c @@ -29,7 +29,7 @@ static const struct pad_config gpio_table[] = { /* CLKRUN# */ PAD_CFG_GPI(GPP_A8, NONE, DEEP), /* EC_IN_RW_OD */ /* ESPI_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), /* ESPI_CLK_R */ /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), -/* PME# */ PAD_CFG_GPO(GPP_A11, 0, DEEP), /* PCH_FP_PWR_EN */ +/* PME# */ PAD_CFG_GPO(GPP_A11, 1, DEEP), /* PCH_FP_PWR_EN */ /* BM_BUSY# */ PAD_CFG_GPI(GPP_A12, NONE, DEEP), /* FPMCU_INT */ /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUSWARN_L */ /* ESPI_RESET# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2), /* ESPI_RESET_L */ |