diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-08-20 14:06:13 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-28 15:15:26 +0000 |
| commit | 903c9764a16fba61bf90187d6f7e2afde37cfec0 (patch) | |
| tree | 613569c7c546b90d941d55374b3f80fa59f30bf8 /src/mainboard/google/zoombini/memory.c | |
| parent | 5dff396befca2241f8323b422cbf6cc5b66a7488 (diff) | |
soc/intel/cannonlake: Change LPDDR4 to MEMCFG
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to
make the infrasturture to handle both LPDDR4 and DDR4 cases in the
future. Consider the case of reading SPD from SMBus other than providing
SPD pointer directly.
BUG=N/A
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28248
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zoombini/memory.c')
| -rw-r--r-- | src/mainboard/google/zoombini/memory.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/google/zoombini/memory.c b/src/mainboard/google/zoombini/memory.c index e1f525590f..802467c44b 100644 --- a/src/mainboard/google/zoombini/memory.c +++ b/src/mainboard/google/zoombini/memory.c @@ -17,10 +17,10 @@ #include <baseboard/gpio.h> #include <compiler.h> #include <gpio.h> -#include <soc/cnl_lpddr4_init.h> +#include <soc/cnl_memcfg_init.h> -static const struct lpddr4_cfg baseboard_lpddr4_cfg = { - .dq_map[LP4_CH0] = { +static const struct cnl_mb_cfg baseboard_lpddr4_cfg = { + .dq_map[DDR_CH0] = { /* * CLK0 goes to package 0 - Bytes[3:0], * CLK1 goes to package 1 - Bytes[7:4] @@ -37,7 +37,7 @@ static const struct lpddr4_cfg baseboard_lpddr4_cfg = { { 0xFF, 0x00 }, }, - .dq_map[LP4_CH1] = { + .dq_map[DDR_CH1] = { /* * CLK0 goes to package 0 - Bytes[3:0], * CLK1 goes to package 1 - Bytes[7:4] @@ -61,8 +61,8 @@ static const struct lpddr4_cfg baseboard_lpddr4_cfg = { * the index = pin number on lpddr4 part * the value = pin number on SoC */ - .dqs_map[LP4_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 }, - .dqs_map[LP4_CH1] = { 3, 2, 0, 1, 7, 5, 6, 4 }, + .dqs_map[DDR_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 }, + .dqs_map[DDR_CH1] = { 3, 2, 0, 1, 7, 5, 6, 4 }, /* Baseboard uses three 100 Ohm rcomp resistors */ .rcomp_resistor = { 100, 100, 100 }, @@ -82,7 +82,7 @@ static const struct lpddr4_cfg baseboard_lpddr4_cfg = { .ect = 0, }; -const struct lpddr4_cfg *__weak variant_lpddr4_config(void) +const struct cnl_mb_cfg *__weak variant_lpddr4_config(void) { return &baseboard_lpddr4_cfg; } |