diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2017-08-28 17:34:36 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-28 18:28:59 +0000 |
| commit | d3e00ab209bde3026082ec6656cefa6dc23de38a (patch) | |
| tree | ae8a1c9a136048afbdc1ab3e3e312ab5541fa0c0 /src/mainboard/google/zoombini/chromeos.fmd | |
| parent | bc652b97172b70374c2dbf05dbc225c793be4308 (diff) | |
google/zoombini: Add new board
Add zoombini board files using cannonlake and FSP 2.0.
Copied most initial files from poppy and cannonlake_rvp.
BUG=b:64395641
BRANCH=None
TEST=Compiles successfully using "./util/abuild/abuild
-p none -t google/zoombini -x -a"
Change-Id: I13ebaae403d08f1b2e6881eeba4dc1787c792b4e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/zoombini/chromeos.fmd')
| -rw-r--r-- | src/mainboard/google/zoombini/chromeos.fmd | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/mainboard/google/zoombini/chromeos.fmd b/src/mainboard/google/zoombini/chromeos.fmd new file mode 100644 index 0000000000..4e23bbfec5 --- /dev/null +++ b/src/mainboard/google/zoombini/chromeos.fmd @@ -0,0 +1,43 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x300000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x2ff000 + } + SI_BIOS@0x300000 0xd00000 { + RW_SECTION_A@0x0 0x368000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x357fc0 + RW_FWID_A@0x367fc0 0x40 + } + RW_SECTION_B@0x368000 0x368000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x357fc0 + RW_FWID_B@0x367fc0 0x40 + } + RW_MISC@0x6d0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 + } + RW_LEGACY(CBFS)@0x700000 0x200000 + WP_RO@0x900000 0x400000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x300000 + } + } + } +} |