diff options
| author | Jes Klinke <jbk@google.com> | 2020-10-30 13:46:39 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-09 07:24:54 +0000 |
| commit | e94f86571c0d327b67ab290e9f01f59a5561c29a (patch) | |
| tree | 0f11d4ec2450ad5992ad88f9518e0d3afe6a5e09 /src/mainboard/google/volteer | |
| parent | d1c0f958d1986a94ac55ae1d196ba286c311b90f (diff) | |
mb/google/volteer: Skip TPM detection except on SPI
Production Volteer devices have Cr50 TPM connected via SPI, depending on
Cr50 firmware version it may or may not support long enough interrupt
pulses for the SoC to safely be able to enable lowest power mode.
Some reworked Volteer devices have had the Cr50 (Haven) TPM replaced
with Dauntless, communicating via I2C. The I2C drivers do not support
being accessed early in ramstage, before chip init and memory
mapping, (tlcl_lib_init() will halt with an error finding the I2C
controller base address.)
Since the Dauntless device under development can be made to support
longer interrupts, or a completely new interrupt signalling mode, there
is no need to try to go through the same discovery as is done via SPI.
This CL will skip the discovery, enabling the S0i3.4 sleep mode in all
cases, on the reworked test devices.
BUG=b:169526865, b:172509545
TEST=abuild -t GOOGLE_VOLTEER2 -c max -x
Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47049
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer')
| -rw-r--r-- | src/mainboard/google/volteer/mainboard.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index acba9722dc..0850e745db 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -96,13 +96,23 @@ static void mainboard_enable(struct device *dev) void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) { int ret; + if (!CONFIG(MAINBOARD_HAS_SPI_TPM_CR50)) { + /* + * Negotiation of long interrupt pulses is only supported via SPI. I2C is only + * used on reworked prototypes on which the TPM is replaced with Dauntless under + * development, it will use long pulses by default, or use the interrupt line in + * a different way altogether. + */ + return; + } + ret = tlcl_lib_init(); if (ret != VB2_SUCCESS) { printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); return; } - if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && cr50_is_long_interrupt_pulse_enabled()) { + if (cr50_is_long_interrupt_pulse_enabled()) { printk(BIOS_INFO, "Enabling S0i3.4\n"); } else { /* |