diff options
| author | John Zhao <john.zhao@intel.com> | 2020-05-19 15:29:07 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:07:24 +0000 |
| commit | f5b33c00166f0e4511de07f0f6ecd639237c5cc2 (patch) | |
| tree | 8cfcea79d1e3d4e0c35c630b26a1664ebe67e6ff /src/mainboard/google/volteer/variants | |
| parent | 3c8cb24fc32d0322da5cfd7fabae3b66ac16470b (diff) | |
mb/google/volteer: Enable D3HotEnable and D3ColdEnable for Volteer
This explicitly enables both of TCSS D3HotEnable and D3ColdEnable
from Volteer devicetree.cb setting.
BUG=:b:146624360
TEST=Built and booted on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1a168ad87169c0f6633704c55c9293aa25710188
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/mainboard/google/volteer/variants')
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 693369542b..02060bdf45 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -136,6 +136,10 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[7]" = "0x0" + # D3Hot and D3Cold for TCSS + register "TcssD3HotEnable" = "1" + register "TcssD3ColdEnable" = "1" + # DP port register "DdiPortAConfig" = "1" # eDP register "DdiPortBConfig" = "0" |