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authorBrandon Breitenstein <brandon.breitenstein@intel.com>2020-04-06 15:34:19 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-05-20 09:13:27 +0000
commitb7911c8e98f493d29acedaf1542f98ad76700f00 (patch)
tree0097d47cae74deb1293dc5b4514f0a8c9fbe5ba8 /src/mainboard/google/volteer/variants
parent71d365d4583064da85e3f6544e2fbd385cf1e8b3 (diff)
mainboard/volteer: Update Aux settings for Port 0
On Volteer port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. This requires 2 changes setting the TcssAuxOri UPD to 1 for port 0 (Bit 0) and configuring AUXP and AUXN GPIOs to Native Function 6 so SOC can control the orientation BUG=b:145220205 BRANCH=NONE TEST=booted Volteer proto 2 and verified that the AUX channels flip when the cable is flipped Change-Id: Ic81adc24d10322cc305bf0fa4c38514468ea0942 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/mainboard/google/volteer/variants')
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb11
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/gpio.c4
2 files changed, 12 insertions, 3 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 273b7a8ccc..fa99de8c8f 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -125,7 +125,16 @@ chip soc/intel/tigerlake
# TCSS USB3
register "TcssXhciEn" = "1"
- register "TcssAuxOri" = "0"
+ register "TcssAuxOri" = "1"
+ register "IomTypeCPortPadCfg[0]" = "0x090E000A"
+ register "IomTypeCPortPadCfg[1]" = "0x090E000D"
+ register "IomTypeCPortPadCfg[2]" = "0x0"
+ register "IomTypeCPortPadCfg[3]" = "0x0"
+ register "IomTypeCPortPadCfg[4]" = "0x0"
+ register "IomTypeCPortPadCfg[5]" = "0x0"
+ register "IomTypeCPortPadCfg[6]" = "0x0"
+ register "IomTypeCPortPadCfg[7]" = "0x0"
+
# DP port
register "DdiPortAConfig" = "1" # eDP
diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c
index 2ca59aa29d..8cbda1c0cb 100644
--- a/src/mainboard/google/volteer/variants/baseboard/gpio.c
+++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c
@@ -215,13 +215,13 @@ static const struct pad_config gpio_table[] = {
/* E9 : USB2_OC0# ==> USB_C1_OC_ODL */
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
/* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */
- PAD_CFG_GPO(GPP_E10, 0, DEEP),
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF6),
/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
/* E12 : SPI1_MISO_IO1 ==> NOT USED */
PAD_NC(GPP_E12, NONE),
/* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */
- PAD_CFG_GPO(GPP_E13, 0, DEEP),
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF6),
/* E14 : DDPC_HPDA ==> SOC_EDP_HPD */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */