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authorFelix Singer <felixsinger@posteo.net>2024-06-27 23:25:32 +0200
committerFelix Singer <felixsinger@posteo.net>2024-06-28 21:43:18 +0000
commit8c1daf97519c64d4e0ac6c1ace3e54a2549a7612 (patch)
tree5583478d3239621fe13f69b883e367fd0c2d1aa8 /src/mainboard/google/volteer/variants
parentdf141f61cc031c0b28385a36b4e636a4a3b32435 (diff)
tgl mainboards: Move SATA related settings into SATA device scope
Change-Id: I03508c50fe56fd85f8bf89f724863e546d4140e9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/google/volteer/variants')
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb13
1 files changed, 6 insertions, 7 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 5df3947e9d..4fdc7b4839 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -141,12 +141,6 @@ chip soc/intel/tigerlake
register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
- # Enable SATA
- register "SataSalpSupport" = "1"
- register "SataPortsEnable[1]" = "1"
- register "SataPortsDevSlp[1]" = "1"
- register "SataPortsEnableDitoConfig[1]" = "1"
-
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
@@ -462,7 +456,12 @@ chip soc/intel/tigerlake
device ref i2c2 on end
device ref i2c3 on end
device ref heci1 on end
- device ref sata on end
+ device ref sata on
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsDevSlp[1]" = "1"
+ register "SataPortsEnableDitoConfig[1]" = "1"
+ end
device ref pcie_rp7 on end
device ref pcie_rp8 on
probe DB_SD SD_GL9755S