diff options
| author | FrankChu <frank_chu@pegatron.corp-partner.google.com> | 2020-12-01 09:54:00 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-12-11 01:10:43 +0000 |
| commit | 71761a383858bbbc31c5092d73579c6b7b5e1692 (patch) | |
| tree | b1ee9f1f34f00f2cc10d93c02e361dcda028a5c7 /src/mainboard/google/volteer/variants | |
| parent | ecf06e5e7531f25ed61d8aae3bdeddea6be2c6d4 (diff) | |
mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin
In order to pass DB type-C Port 1 USB2 eye diagram, DB USB2 PHY register needs
to be overridden.
port#1
PortUsb20Enable=1
Usb2PhyPetxiset=3
Usb2PhyTxiset=2
Usb2PhyPredeemp=7
Usb2PhyPehalfbit=1
BUG=b:173676539
BRANCH=None
TEST=emerge-volteer coreboot chromeos-bootimage
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants')
| -rw-r--r-- | src/mainboard/google/volteer/variants/delbin/overridetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index c0eaedb25c..577404737b 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -44,6 +44,14 @@ chip soc/intel/tigerlake }, }, }" + #These settings improve the USB2 Port1 eye diagram + register "usb2_ports[3]" = "{ + .enable = 1, + .tx_bias = USB2_BIAS_28P15MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_56P3MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Acoustic settings register "AcousticNoiseMitigation" = "1" |