From 71761a383858bbbc31c5092d73579c6b7b5e1692 Mon Sep 17 00:00:00 2001 From: FrankChu Date: Tue, 1 Dec 2020 09:54:00 +0800 Subject: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin In order to pass DB type-C Port 1 USB2 eye diagram, DB USB2 PHY register needs to be overridden. port#1 PortUsb20Enable=1 Usb2PhyPetxiset=3 Usb2PhyTxiset=2 Usb2PhyPredeemp=7 Usb2PhyPehalfbit=1 BUG=b:173676539 BRANCH=None TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: FrankChu Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48194 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/volteer/variants/delbin/overridetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/google/volteer/variants') diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index c0eaedb25c..577404737b 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -44,6 +44,14 @@ chip soc/intel/tigerlake }, }, }" + #These settings improve the USB2 Port1 eye diagram + register "usb2_ports[3]" = "{ + .enable = 1, + .tx_bias = USB2_BIAS_28P15MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_56P3MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Acoustic settings register "AcousticNoiseMitigation" = "1" -- cgit v1.2.3