diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-21 03:46:58 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-16 19:50:16 +0000 |
| commit | cf2f7005f623ab8819fc8f893b7cfe7b27d8f9a2 (patch) | |
| tree | a2db8d2d67717437bd412a9e0668cbb7e96ed740 /src/mainboard/google/volteer/variants/voxel | |
| parent | e31bfef2b0631ec6e8ab5e659a64adcaca200de3 (diff) | |
mb/google/volteer: do UART pad config at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: I5e07584d7857052c7a9388331a475f5a073af038
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants/voxel')
| -rw-r--r-- | src/mainboard/google/volteer/variants/voxel/gpio.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/voxel/gpio.c b/src/mainboard/google/volteer/variants/voxel/gpio.c index d6df489f0d..b8d1f39936 100644 --- a/src/mainboard/google/volteer/variants/voxel/gpio.c +++ b/src/mainboard/google/volteer/variants/voxel/gpio.c @@ -237,6 +237,11 @@ const struct pad_config *variant_override_gpio_table(size_t *num) /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ |