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authorSheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>2020-11-23 16:06:44 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-11-24 16:24:20 +0000
commitc5395bc95d28927b81cbf97741cf80fa0e0e78c1 (patch)
tree5746afe5793e5a03091ab0f647d1ea192d85d954 /src/mainboard/google/volteer/variants/voxel
parent17a798b68cc6d475d5d0c14e1a4a39b14754203c (diff)
mb/google/volteer/var/voxel: Update DPTF parameters
update the DPTF parameters received from the thermal team. BUG=b:167523658 TEST=emerge-volteer coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47858 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants/voxel')
-rw-r--r--src/mainboard/google/volteer/variants/voxel/overridetree.cb12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
index dd29553e82..9c4aa47d2f 100644
--- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
@@ -23,22 +23,22 @@ chip soc/intel/tigerlake
## Active Policy
register "policies.active" = "{
[0] = {.target = DPTF_CPU,
- .thresholds = {TEMP_PCT(94, 100),}},
+ .thresholds = {TEMP_PCT(98, 100),}},
[1] = {.target = DPTF_TEMP_SENSOR_2,
.thresholds = {TEMP_PCT(64, 100),
TEMP_PCT(60, 90),
TEMP_PCT(56, 80),
TEMP_PCT(52, 70),
- TEMP_PCT(48, 60),
- TEMP_PCT(44, 50),
- TEMP_PCT(40, 40),}}}"
+ TEMP_PCT(47, 60),
+ TEMP_PCT(42, 50),
+ TEMP_PCT(35, 40),}}}"
## Passive Policy
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000),
- [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 54, 6000),
+ [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 52, 6000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}"
## Critical Policy
@@ -58,7 +58,7 @@ chip soc/intel/tigerlake
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,},
- .pl2 = {.min_power = 15000,
+ .pl2 = {.min_power = 51000,
.max_power = 51000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,