diff options
| author | Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> | 2020-10-06 16:52:32 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-10-12 17:22:28 +0000 |
| commit | 854848c39d83ff3e3c9812a45701cb1eb3a11254 (patch) | |
| tree | 1f4251565a172211657ce1717784a882371e2b72 /src/mainboard/google/volteer/variants/voxel | |
| parent | 1447c4310e6c31f1d0f536f0a56ca2184b840dd2 (diff) | |
mb/google/volteer/var/voxel: disable DdiPortHpd
GPP_A19 and GPP_A20 set no connection, disables DdiPort1Hpd and DdiPort2Hpd
BUG=b:169690329
TEST=build and verify type-c(C0/C1) port functional normally
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46069
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: TH Lin <t.h_lin@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants/voxel')
| -rw-r--r-- | src/mainboard/google/volteer/variants/voxel/overridetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 8ce687567b..d7a265b010 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/tigerlake + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" register "tcc_offset" = "5" # TCC of 95 register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ |